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and TUD, respectively.<br />

6. Principal investigator for NXP, and definition of contributions for NXP<br />

and TUD for the Tera-Scale Multi-Core Processor Architecture (TSAR)<br />

MEDEA+ project, 2008-2011 (3 years). 3 and 4.5 person years at NXP<br />

and TUD, respectively.<br />

7. Principal investigator for NXP, and definition of the NXP and TUD contributions<br />

for the 3D-TSV Integration for Multimedia and Mobile applications<br />

(3DIM3) CATRENE project, 2009-2011. 34 and 18 person years at<br />

NXP and TUD, respectively.<br />

8. Definition of the NXP and TUD contributions for the Communication-<br />

Centric Heterogeneous Multi-Core Architectures (COMCAS) CATRENE<br />

project, 2009-2011 (3 years). 24 and 12.3 person years at NXP and TUD,<br />

respectively.<br />

9. Principal investigator for NXP, and definition of NXP and TUD contributions<br />

for the Scalable Low-Power Embedded Platforms (SCALOPES)<br />

Artemis project, 2009-2010 (2 years). 33 and 9 person years at NXP and<br />

TUD, respectively.<br />

10. Principal investigator for NXP, and definition of the NXP and TUD contributions<br />

for the Industrial Exploitation Of The Genesys Cross-Domain<br />

Architecture (INDEXYS) 2008 Artemis project, 2009-2011 (2 years). 5<br />

and 2.5 person years at NXP and TUD, respectively.<br />

11. Principal co-investigator for TUD, and definition of TUD contributions<br />

for the Computing Fabric for high performance Applications (COBRA)<br />

2009 Catrene project, 2010-2012 (3 years). 15 person years at TUD.<br />

12. Principal investigator for the FP7-ICT-2011-7 project Time-predictable<br />

Multi-Core Architecture for Embedded <strong>Systems</strong> (T-CREST), grant agreement<br />

number 288008, 2011-2014 (3 years). 5.1 person years.<br />

13. Principal investigator for the FP7-ICT-2011-7 project Self adaptive heterogeneous<br />

manycore based on Flexible Tiles (Flextiles), grant agreement<br />

number 288248. 4.6 person years.<br />

6.2 Other Professional Activities<br />

1. 2007, External project proposal examinator for the System on Chip programme,<br />

Austrian Research Promotion Agency.<br />

2. 2008, Gave a two-day course on networks on chip for the European patent<br />

office (EPO) at Rijswijk.<br />

3. 2009, External project proposal examinator for the Swiss National Science<br />

Foundation.<br />

4. 2009, External project proposal examinator for the Estonian Science Foundation.<br />

5. 2009, Member of assessment committee for professor position, Technical<br />

University of Denmark.<br />

6. 2009, Member of assessment committee (“benoemingsadviescommissie”)<br />

for professor position, Technical University of Delft.<br />

7. 2010, External project proposal examinator for the System on Chip pro-<br />

28

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