CV - Electronic Systems
CV - Electronic Systems
CV - Electronic Systems
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8. Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, and<br />
Marco Bekooij. Applying dataflow analysis to dimension buffers for guaranteed<br />
performance in networks on chip. In Proc. Int’l Symposium on<br />
Networks on Chip (NOCS), pages 211–212, April 2008.<br />
9. Muhammad Aqeel Wahlah and Kees Goossens. Hardwired NOC infrastructure<br />
with integrated configuration and functional architectures.<br />
In Proc. Annual Workshop on Circuits, <strong>Systems</strong> and Signal Processing<br />
(ProRisc), November 2008.<br />
10. R. Benjaminsen, F. Duarte, J. Huisken, and K. Goossens. Gate-level<br />
power analysis of on-chip communication infrastructures for biomedical<br />
applications. In Proc. Annual Workshop on Circuits, <strong>Systems</strong> and Signal<br />
Processing (ProRisc), November 2009.<br />
11. Aleksandar Milutinović, Anca Molnos, Kees Goossens, and Gerard J.M.<br />
Smit. Dynamic voltage and frequency scaling and adaptive body biasing<br />
for active and leakage power reduction in MPSOC: a literature overview.<br />
In Proc. Annual Workshop on Circuits, <strong>Systems</strong> and Signal Processing<br />
(ProRisc), Veldhoven, The Netherlands, November 2009.<br />
12. Ashkan Beyranvand Nejad, Kees Goossens, Johan Walters, and Bart Kienhuis.<br />
Mapping KPN models of streaming applications on a network-onchip<br />
platform. In Proc. Annual Workshop on Circuits, <strong>Systems</strong> and<br />
Signal Processing (ProRisc), November 2009.<br />
13. Radu Stefan and Kees Goossens. NoC security using multipath routing.<br />
In Proc. Annual Workshop on Circuits, <strong>Systems</strong> and Signal Processing<br />
(ProRisc), November 2009.<br />
14. Muhammad Aqeel Wahlah and Kees Goossens. Run-time FPGA testing<br />
using hardwired network on chip. In Proc. Annual Workshop on Circuits,<br />
<strong>Systems</strong> and Signal Processing (ProRisc), November 2009.<br />
15. Muhammad Aqeel Wahlah and Kees Goossens. 3-tier reconfiguration<br />
model for FPGAs using hardwired network on chip. In Proc. Int’l Conference<br />
on Field-Programmable Technology (FPT), December 2009.<br />
16. Erik Larsson, Bart Vermeulen, and Kees Goossens. Checking pipelined<br />
distributed global properties at post-silicon debug. In DAC Workshop on<br />
Diagnostic Services in Network-on-Chips (DSNoC), June 2010.<br />
17. Davit Mirzoyan, Benny Akesson, and Kees Goossens. Impact of process<br />
variations on the throughput of real-time applications in multiprocessor<br />
systems-on-chip. In Proc. Annual Workshop on PROGram for Research<br />
on Embedded <strong>Systems</strong> & Software (Progress), November 2010.<br />
18. Ashkan Beyranvand Nejad, Matias Escudero Martinez, and Kees Goossens.<br />
On-chip interconnect protocol stack exploration for FPGA board-to-board<br />
bridging. In Proc. Annual Workshop on PROGram for Research on Embedded<br />
<strong>Systems</strong> & Software (Progress), November 2010.<br />
19. Karthik Chandrasekar, Benny Akesson, and Kees Goossens. Modeling<br />
and optimizing power for a real-time SDRAM controller. In Proc. Annual<br />
Workshop on PROGram for Research on Embedded <strong>Systems</strong> & Software<br />
(Progress), November 2010.<br />
20. Andrew Nelson, Orlando Moreira, Sander Stuijk, Anca Molnos, Kees<br />
19
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