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software virtualization for the reconfigurable multicore platform. In<br />

Proc. Int’l Conference on Embedded and Ubiquitous Computing (EUC),<br />

December 2012. Invited paper.<br />

Almost all of these were peer reviewed.<br />

4.6 Special sessions and tutorials<br />

1. Saddek Bensalem, Kees Goossens, Christoph M. Kirsch, Roman Obermaisser,<br />

Edward A. Lee, and Joseph Sifakis. Time-predictable and composable<br />

architectures for dependable embedded systems. In Proc. ACM<br />

Int’l Conference on Embedded software (EMSOFT), EMSOFT ’11, pages<br />

351–352, New York, NY, USA, October 2011. ACM.<br />

2. Benny Akesson, Po-Chun Huang, Fabien Clermidy, Denis Dutoit, Kees<br />

Goossens, Yuan-Hao Chang, Tei-Wei Kuo, Pascal Vivet, and Drew Wingard.<br />

Memory controllers for high-performance and real-time MPSoCs — Requirements,<br />

architectures, and future trends. In Int’l Conf. on Hardware/Software<br />

Codesign and System Synthesis (CODES+ISSS), pages 3–<br />

12, October 2011.<br />

4.7 Local Conferences, Posters, etc.<br />

1. K. G. W. Goossens. Integrating hardware description languages and proof<br />

systems. In IFIP 12th World Computer Congress, September 1992.<br />

2. Wim Verhaegh, Gertjan Arnoldussen, Kees Goossens, and Marc Heijligers.<br />

Phideo: architectural synthesis for high-throughput digital signal processing.<br />

Philips Research Bulletin on IC Design, (31):9–11, 1997.<br />

3. Edwin Rijpkema, Kees Goossens, and Paul Wielage. A router architecture<br />

for networks on silicon. In Proceedings of Progress 2001, 2nd Workshop<br />

on Embedded <strong>Systems</strong>, Veldhoven, the Netherlands, October 2001.<br />

4. Xiao Ru, John Dielissen, Christer Svensson, and Kees Goossens. Synchronous<br />

latency-insensitive design in Æthereal NoC. Future Interconnects<br />

and Network on Chip workshop at Design, Automation and Test in<br />

Europe Conference and Exhibition (DATE), March 2006.<br />

5. Kees Goossens. Multiple use-cases for a network-on-chip design flow. Future<br />

Interconnects and Network on Chip workshop at Design, Automation<br />

and Test in Europe Conference and Exhibition (DATE), March 2006.<br />

6. Pengwei Ren, Alexandre M. Amory, Erik Jan Marinissen, Kees Goossens,<br />

Sandeep K. Goel, Georgi N. Gaydadjiev, Marcelo Lubaszewski, and Fernando<br />

Moraes. Test wrapper design that allows a core to be tested via a<br />

network-on-chip or other functional interconnect. Diagnostic Services in<br />

Networks-on-Chips workshop at Design, Automation and Test in Europe<br />

Conference and Exhibition (DATE), April 2007.<br />

7. Aleksandar Milutinović, Kees Goossens, and Gerard J.M. Smit. Slack<br />

exploitation for aggressive dynamic power reduction in SoC. In Proc.<br />

Annual Workshop on Circuits, <strong>Systems</strong> and Signal Processing (ProRisc),<br />

Veldhoven, The Netherlands, November 2007.<br />

18

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