CV - Electronic Systems

10. Wouter Loeffen “Automated Generation of IP Core Wrappers for Faster
SoC Integration using High Level Synthesis”, TUE, 2012.
11. Adriaan van Buuren “Dynamic loading and task migration for streaming
applications on a composable system on chip” TUD, 2012. r
7.9 Bachelor Project Supervision
I have (co)-supervised the following BSc students for their bachelor end projects.
1. Ruud Bauhaus, TUE, on implementing H263 video encoding on Comp-
SOC, 2011.
2. Marco Rompen, TUE, on implementing a real-time control algorithm on
CompSOC, 2012.
8 Committees
• Examination committee embedded systems 1 October 2010 - 30 September
2014.
• Education committee electrical engineering faculty as of 1 December 2010.
• Advisory committee (Benoemingsadviescommissie) for the TU Delft “Computer
Engineering” Chair Professor position, 2009.
• Advisory committee for a Assistant/Associate Professor System-on-Chip
position at the Danish Technical University (DTU), 2009.
• Advisory committee (Benoemingsadviescommissie) for the TU Delft “Computer
Engineering” Chair Professor position, 2011.
9 Research Interests
Having worked in varied research fields is, I believe, one of my strengths. In
academia, I started with software engineering and pure mathematics, and then
moved to formal hardware verification using logics and proof systems. After joining
Philips, after working on hardware synthesis and associated high-throughput
hardware architectures, I shifted to system-level design methods and on-chip
communication protocols. Many of these diverse interests are combined in my
current networks-on-chip research.
The focus of the Æthereal research effort has been on defining a network
on chip with communication services with predictable performance to enable a
design flow that reduces the effort to design and program SOCs. As of 2004,
memory controllers with guaranteed performance have been an additional topic
of interest, to enlarge the scope of predictable communication to include predictable
storage. My long-term goal is to be be able to construct SOCs (including
software) with predictable performance, based on compositional performance
(quality of service) models that are enabled by appropriate hardware and
software concepts and architectures.
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