3-Phase BLDC Motor Control with Sensorless Back EMF ... - Freescale

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Hardware 6.4 High Voltage Hardware Set The system configuration is shown in Figure 6-3. L N PE 100 - 240VAC 49 - 61 Hz U2 MB1 J11.1 J11.2 Black White Red Not Connected 3ph AC/BLDC High Voltage +12VDC GND 40w flat ribbon cable Power Stage J14 J1 Board J2 J30 (P1) J13.1 J13.2 J13.3 SM40V J5 Motor-Brake SG40N Red White Black Not Connected ECMTRHIVBLDC Optoisolation 3-Phase BLDC Motor Control, Rev. 1 40w flat ribbon cable 32 Freescale Semiconductor Preliminary U3 ECOPT ECOPTHIVACBLDC JP1.1 JP1.2 Figure 6-3. High Voltage Hardware System Configuration All the system parts are supplied and documented according the following references: U1 Controller Board • U1 - Controller Board for 56F805: — supplied as: 56F805EVM — described in: Evaluation Module Hardware User’s Manual • or U1 - Controller Board for 56F803: — supplied as: 56F803EVM — described in: 56F803 Evaluation Module Hardware User’s Manual • U2 - 3 ph AC/BLDC High Voltage Power Stage — supplied in kit with Optoisolation Board as: ECOPTHIVACBLDC — described in: 3 Phase Brushless DC High Voltage Power Stage • U3 - Optoisolation Board — supplied with 3 ph AC/BLDC High Voltage Power Stage as: ECOPTHIVACBLDC — or supplied alone as: ECOPT - ECOPT optoisolation board — described in: Optoisolation Board User’s Manual DSP56805EVM (DSP56803EVM) Warning: It is strongly recommended to use opto-isolation (optocouplers and optoisolation amplifiers) during the development time to avoid any damage to the development equipment. • MB1 Motor-Brake SM40V + SG40N — supplied as: ECMTRHIVBLDC Information for all boards and documents can be found at: www.freescale.com
7. SW Design 3-Phase BLDC Motor Control, Rev. 1 Main SW Flow Chart This section describes the design of the software blocks of the drive. The software will be described in terms of: • Main Software Flow Chart • Data Flow • State Diagram For more information of the used control technique see Section 5. 7.1 Main SW Flow Chart The main software flow chart incorporates the Main routine entered from Reset, and interrupt states. The Main routine includes the initialization of the device and the main loop. It is shown in Figure 7-1 and Figure 7-2. The main loop incorporates Application State Machine - the highest SW level which precedes settings for other software levels, BLDC motor Commutation Control, Speed Control, Alignment Current Control, etc. The inputs of Application State Machine are Run/Stop Switch state, Required Speed Omega and Drive Fault Status. Required Mechanical Speed can be set from PC master software or manually with Up/Down buttons. Commutation Control proceeds BLDC motor commutation with the states described in Section 5 and Section 7.3.4. The Speed Control is detailed description is in sections Section 7.2.3 and Section 7.3.5. Alignment Current Control is described in Section 7.2.4 and Section 7.3.6. Run/Stop switch is checked to provide an input for Application State Machine (ApplicationMode Start or Stop). The interrupt subroutines provide commutation Timer services, ADC starting in the PWM reload interrupt, ADC service, ADC Zero Crossing checking, Limit analog values handling, overcurrent and overvoltage PWM fault handler. The Commutation Timer ISR is used for Commutation Timing and Commutation Control and Zero Crossing Checking proceeding. The Speed/Alignment Timer ISR is used for Speed regulator time base and for Alignment stage duration timing. The PWM Reload ISR is used to evaluate BEMF Zero Crossing, start ADC conversion and memorize Zero Crossing sampling time T_ZCSample. The ADC Complete ISR is used to read voltages, current and temperature samples from the ADC. It also sets Current control and when the Current Control setting is enabled. The other interrupts in Figure 7-2 are used for System Fault handling and setting of Required Mechanical Speed input for Application State Machine (ApplicationMode Start or Stop). Freescale Semiconductor 33 Preliminary
Page 1 and 2: Freescale Semiconductor Application
Page 3 and 4: Table 2-1. Memory Configuration 56F
Page 5 and 6: Stator Stator winding (in slots) Sh
Page 7 and 8: 3.3 Why Sensorless Control? 3-Phase
Page 9 and 10: 3.4.1 Mathematical Model The follow
Page 11 and 12: 3.6 Back-EMF Sensing Circuit 0 30 6
Page 13 and 14: • Running on one of three optiona
Page 15 and 16: Power line PC Master START STOP UP
Page 17 and 18: PWM1 S At PWM2 S Ab PWM3 S Bt PWM4
Page 19 and 20: 3-Phase BLDC Motor Control, Rev. 1
Page 23 and 24: 5.4.2.2 Running - Commutation Times
Page 27 and 28: Phase Back-EMFs Back-EMF Zero Cross
Page 31: 6.3 Low Voltage Hardware Set The sy
Page 35 and 36: Interrupt Up Button Up Button ISR:
Page 37 and 38: Protection processes are shown in F
Page 39 and 40: 7.3.1 Main SW States - General Over
Page 41 and 42: • Starting (Back-EMF Acquisition)
Page 43 and 44: 7.3.4.3 Commutation Control - Set R
Page 45 and 46: 7.3.6 State Diagram - Process Curre
Page 49 and 50: 11. Setting of SW parameters for ot
Page 51 and 52: 11.2.2 Start-up Periods The constan
Page 53 and 54: Coef_CmtPrecompLShft Coef_CmtPrecom

3-Phase BLDC Motor Control with Sensorless Back EMF ... - Freescale

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