MC68HC908JW32, MC68HC908JW32 - Data Sheet - Freescale

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General Description • External asynchronous interrupt pin with internal pull-up (IRQ) • 48-pin quad flat non-leaded package (QFN) 1.3 MCU Block Diagram CPU REGISTERS M68HC08 CPU ARITHMETIC/LOGIC UNIT (ALU) CONTROL AND STATUS REGISTERS — 96 BYTES USER FLASH — 32,768 BYTES USER RAM — 1,024 BYTES MONITOR ROM — 1,472 BYTES USER FLASH VECTOR SPACE — 48 BYTES (1)(2) RST (1)(3) IRQ VDD VSS VDDPLL VSSPLL REG25V REG33V VSS33 OSCILLATORS AND CLOCK GENERATOR MODULE INTERNAL RC OSCILLATOR OSC1 X-TAL OSCILLATOR OSC2 CGMXFC PHASE-LOCKED LOOP SYSTEM INTEGRATION MODULE EXTERNAL INTERRUPT MODULE COMPUTER OPERATING PROPERLY MODULE POWER-ON RESET MODULE POWER INTERNAL REGULATOR INTERNAL BUS KEYBOARD INTERRUPT MODULE 2-CHANNEL TIMER INTERFACE MODULE TIMEBASE MODULE BREAK MODULE LOW-VOLTAGE INHIBIT MODULE PS2 CLOCK GENERATOR MODULE SERIAL PERIPHERAL INTERFACE MODULE USB MODULE USB USB ENDPOINT FS Figure 1-1. MC68HC908JW32 Block Diagram MC68HC908JW32 Data Sheet, Rev. 6 18 Freescale Semiconductor TRANSCEIVER DDRA DDRB DDRD PORTA PORTB PORTD PTA7/KBA7 (3) PTA6/KBA6 (3) PTA5/KBA5 (3) PTA4/KBA4 (3) PTA3/KBA3 (3) PTA2/KBA2 (3) PTA1/KBA1 (3) PTA0/KBA0 (3) PTB5 (2)(4) PTB1 (2)(4) PTB0 (2)(4) PTB6 (2)(4)(5) PTB7 (2)(4)(5) PTB4 (2)(4)(5) PTB3 (2)(4)(5) PTB2 (2)(4)(5) PTC3 PTC2/T1CH1 PTC1/TCLK1 PTC0/T1CH0 PTD7 (2) PTD6 PTD5 PTD4 PTD3 (2) PTD2 (2) PTD1 PTD0 PTE7/SS PTE6/MISO PTE5/MOSI PTE4/SPCLK PTE3/D– (2)(4) PTE2/PS2CLK/D+ (2)(4) (1) Pin contains integrated pullup device. (2) Pin contains configurable pullup device. (3) Pin contains integrated pullup device when configured as KBI. (4) Pin is open-drain when configured as output, with high current capability. (5) Pin available on 52-pin LQFP only. DDRC DDRE PORTC PORTE
1.4 Pin Assignments PTA0/KBA0 PTC1/TCLK1 PTC3 PTB7 PTB6 PTB5 PTB4 PTC0/T1CH0 PTE7/SS PTE6/MISO PTE5/MOSI PTE4/SPCLK NC 1 2 3 4 5 6 7 8 9 10 11 12 13 PTA1/KBA1 52 14 PTD0 PTA2/KBA2 51 15 PTD1 PTA3/KBA3 50 16 PTD2 PTA4/KBA4 49 17 PTD3 V SS 48 18 PTD4 REG25V 47 19 PTD5 V DD 46 20 PTD6 Figure 1-2. 52-Pin LQFP Pin Assignment MC68HC908JW32 Data Sheet, Rev. 6 Pin Assignments Freescale Semiconductor 19 PTC2/T1CH1 45 21 NC PTA5/KBA5 44 22 NC PTA6/KBA6 43 23 NC IRQ 42 24 NC RESET 41 25 NC PTA7/KBA7 40 26 PTD7 39 38 37 36 35 34 33 32 31 30 29 28 27 NC = No Connection V DDPLL CGMXFC VSSPLL REG33V PTE3/D– PTE2/PS2CLK/D+ V SS33 PTB3 PTB2 PTB1 PTB0 OSC2 OSC1
Page 1: MC68HC908JW32 Data Sheet M68HC08 Mi
Page 4 and 5: The following revision history tabl
Page 6 and 7: List of Chapters MC68HC908JW32 Data
Page 8 and 9: Table of Contents Chapter 3 Configu
Page 10 and 11: Table of Contents 6.5.3 Reset . . .
Page 12 and 13: Table of Contents 10.12.1 MISO (Mas
Page 14 and 15: Table of Contents Chapter 16 Comput
Page 16 and 17: Table of Contents MC68HC908JW32 Dat
Page 20 and 21: General Description 1.5 Clock Tree
Page 22 and 23: General Description V DD V SS must
Page 24 and 25: General Description MC68HC908JW32 D
Page 26 and 27: Memory $0000 ↓ $005F $0060 ↓ $0
Page 28 and 29: Memory Addr. Register Name Bit 7 6
Page 34 and 35: Memory Table 2-1 is a list of vecto
Page 36 and 37: Memory 2.5.2 FLASH Control Register
Page 38 and 39: Memory This program sequence is rep
Page 40 and 41: Memory 2.5.7 FLASH Block Protect Re
Page 42 and 43: Configuration Registers (CONFIG) 3.
Page 44 and 45: Configuration Registers (CONFIG) MC
Page 46 and 47: Central Processor Unit (CPU) 15 15
Page 48 and 49: Central Processor Unit (CPU) 4.3.5
Page 50 and 51: Central Processor Unit (CPU) 4.7 In
Page 52 and 53: Central Processor Unit (CPU) Source
Page 54 and 55: Central Processor Unit (CPU) Source
Page 56 and 57: 56 Freescale Semiconductor MC68HC90
Page 58 and 59: Clock Generator Module (CGM) OSC2 O
Page 60 and 61: Clock Generator Module (CGM) 5.3.3
Page 62 and 63: Clock Generator Module (CGM) The fo
Page 64 and 65: Clock Generator Module (CGM) 9. Pro
Page 66 and 67: Clock Generator Module (CGM) 5.4 I/
Page 68 and 69:
Clock Generator Module (CGM) BCS
Page 70 and 71:
Clock Generator Module (CGM) 5.5.3
Page 72 and 73:
Clock Generator Module (CGM) VCO cl
Page 74 and 75:
Clock Generator Module (CGM) 5.8.3
Page 76 and 77:
System Integration Module (SIM) RES
Page 78 and 79:
System Integration Module (SIM) 6.2
Page 80 and 81:
System Integration Module (SIM) At
Page 82 and 83:
System Integration Module (SIM) opt
Page 84 and 85:
System Integration Module (SIM) If
Page 86 and 87:
System Integration Module (SIM) Pri
Page 88 and 89:
System Integration Module (SIM) IAB
Page 90 and 91:
System Integration Module (SIM) 6.7
Page 92 and 93:
System Integration Module (SIM) MC6
Page 94 and 95:
Monitor Mode (MON) 1 µF 1 µF DB9
Page 96 and 97:
Monitor Mode (MON) Enter monitor mo
Page 98 and 99:
Monitor Mode (MON) FROM HOST ECHO R
Page 100 and 101:
Monitor Mode (MON) Table 7-7. IWRIT
Page 102 and 103:
Monitor Mode (MON) During monitor m
Page 104 and 105:
Monitor Mode (MON) The control and
Page 106 and 107:
Monitor Mode (MON) The coding examp
Page 108 and 109:
Timer Interface Module (TIM) 8.4 Fu
Page 110 and 111:
Timer Interface Module (TIM) 8.4.3
Page 112 and 113:
Timer Interface Module (TIM) Use th
Page 114 and 115:
Timer Interface Module (TIM) If TIM
Page 116 and 117:
Timer Interface Module (TIM) TRST
Page 118 and 119:
Timer Interface Module (TIM) Addres
Page 120 and 121:
Timer Interface Module (TIM) NOTE W
Page 122 and 123:
Timer Interface Module (TIM) MC68HC
Page 124 and 125:
Timebase Module (TBM) ÷ 2 ÷ 2 88-
Page 126 and 127:
Timebase Module (TBM) 9.6 Low-Power
Page 128 and 129:
Serial Peripheral Interface Module
Page 130 and 131:
Page 132 and 133:
Page 134 and 135:
Page 136 and 137:
Page 138 and 139:
Page 140 and 141:
Page 142 and 143:
Page 144 and 145:
Page 146 and 147:
Page 148 and 149:
USB 2.0 FS Module 11.3 USB Module A
Page 150 and 151:
USB 2.0 FS Module 11.3.4 USB Reques
Page 152 and 153:
USB 2.0 FS Module There are 64-byte
Page 154 and 155:
USB 2.0 FS Module Addr. Register Na
Page 156 and 157:
USB 2.0 FS Module 11.5.2 USB Status
Page 158 and 159:
USB 2.0 FS Module USBRSTIE — USB
Page 160 and 161:
USB 2.0 FS Module SIZE[1:0] — Buf
Page 162 and 163:
USB 2.0 FS Module 11.5.8 USB Interf
Page 164 and 165:
PS2 Clock Generator (PS2CLK) CLK Ou
Page 166 and 167:
PS2 Clock Generator (PS2CLK) MC68HC
Page 168 and 169:
Input/Output (I/O) Ports Addr. Regi
Page 170 and 171:
Input/Output (I/O) Ports Port Bit D
Page 172 and 173:
Input/Output (I/O) Ports 13.3 Port
Page 174 and 175:
Page 176 and 177:
Page 178 and 179:
Page 180 and 181:
Input/Output (I/O) Ports PTE3 pin f
Page 182 and 183:
Page 184 and 185:
Input/Output (I/O) Ports MC68HC908J
Page 186 and 187:
External Interrupt (IRQ) When set,
Page 188 and 189:
External Interrupt (IRQ) 14.5 PTE3/
Page 190 and 191:
External Interrupt (IRQ) MC68HC908J
Page 192 and 193:
Keyboard Interrupt Module (KBI) 15.
Page 194 and 195:
Keyboard Interrupt Module (KBI) 15.
Page 196 and 197:
Keyboard Interrupt Module (KBI) MC6
Page 198 and 199:
Computer Operating Properly (COP) T
Page 200 and 201:
Computer Operating Properly (COP) 1
Page 202 and 203:
Low-Voltage Inhibit (LVI) V DD LOW
Page 204 and 205:
Low-Voltage Inhibit (LVI) MC68HC908
Page 206 and 207:
Break Module (BRK) 18.3 Functional
Page 208 and 209:
Break Module (BRK) BRKE — Break E
Page 210 and 211:
Break Module (BRK) MC68HC908JW32 Da
Page 212 and 213:
Electrical Specifications 19.3 Func
Page 214 and 215:
Electrical Specifications Pullup re
Page 216 and 217:
Electrical Specifications 19.10 Tim
Page 218 and 219:
Electrical Specifications SS INPUT
Page 220 and 221:
Electrical Specifications MC68HC908
Page 232:
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MC68HC908JW32, MC68HC908JW32 - Data Sheet - Freescale

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