MC68HC908JW32, MC68HC908JW32 - Data Sheet - Freescale

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Memory Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 Timer 1 Counter Register Low (T1CNTL) Timer 1 Counter Modulo Register High (T1MODH) Timer 1 Counter Modulo Register Low (T1MODL) Timer 1 Channel 0 Status and Control Register (T1SC0) Timer 1 Channel 0 Register High (T1CH0H) Timer 1 Channel 0 Register Low (T1CH0L) Timer 1 Channel 1 Status and Control Register (T1SC1) Timer 1 Channel 1 Register High (T1CH1H) Timer 1 Channel 1 Register Low (T1CH1L) Keyboard Status and Control Register (KBSCR) Keyboard Interrupt Enable Register (KBIER) Timebase Control Register (TBCR) PS2 Clock Generator Control and Satus Register (PS2CSR) Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Write: Reset: 0 0 0 0 0 0 0 0 Read: Write: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Reset: 1 1 1 1 1 1 1 1 Read: Write: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset: 1 1 1 1 1 1 1 1 Read: CH0F Write: 0 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Reset: 0 0 0 0 0 0 0 0 Read: Write: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Reset: Indeterminate after reset Read: Write: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset: Indeterminate after reset Read: CH1F Write: 0 CH1IE MC68HC908JW32 Data Sheet, Rev. 6 28 Freescale Semiconductor 0 MS1A ELS1B ELS1A TOV1 CH1MAX Reset: 0 0 0 0 0 0 0 0 Read: Write: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Reset: Indeterminate after reset Read: Write: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset: Indeterminate after reset Read: 0 0 0 0 KEYF 0 Write: ACKK IMASKK MODEK Reset: 0 0 0 0 0 0 0 0 Read: Write: KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 Reset: 0 0 0 0 0 0 0 0 Read: TBIF 0 TBR2 TBR1 TBR0 Write: TACK TBIE TBON R Reset: 0 0 0 0 0 0 0 0 Read: PSTATUS Write: PS2IF PRE CSEL1 CSEL0 PS2IEN CLKEN PS2EN Reset: 0 0 0 0 0 0 0 0 = Unimplemented R = Reserved U = Unaffected by reset Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 7)
$001A Port Option Control Register 1 (POCR1) Read: Write: MC68HC908JW32 Data Sheet, Rev. 6 Monitor ROM Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $001B $001C $001D $001E $001F $0020 to $003D $003E Port Option Control Register 2 (POCR2) IRQ Option Control Register (IOCR) Configuration Register 2 (CONFIG2) IRQ Status and Control Register (ISCR) Configuration Register (CONFIG) † LEDB7 LEDB6 LEDB5 LEDB4 LEDB3 LEDB2 LEDB1 LEDB0 Reset: 0 0 0 0 0 0 0 0 Read: 0 0 Write: PTD7PD PTD3PD PTD2PD DPPULLEN PTE3P PTE2P Reset: 0 0 0 0 0 0 0 0 Read: 0 0 0 0 0 PTE3IF Write: Reset: Read: STOP_ Write: XCLKEN STOP_RC CLKEN PTE3IE IRQPD R VREG33D URSTD Reset: 0 0 0 0 0 0 0 0 Read: 0 0 0 0 IRQF 0 Write: ACK IMASK MODE Reset: 0 0 0 0 0 0 0 0 Read: COPRS LVISTOP LVIRSTD LVIPWRD SSREC STOP COPD Write: † One-time writable register after each reset. Reserved Pullup Control Register (PULLCR) $003F Reserved $0040 $0041 $0042 $0043 USB Endpoint 0 Data Register 0 (UE0D0) USB Endpoint 0 Data Register 1 (UE0D1) USB Endpoint 0 Data Register 2 (UE0D2) USB Endpoint 0 Data Register 3 (UE0D3) Reset: 0 0 0 0 0 0 0 0 Read: Write: R R R R R R R R Read: PULL7EN PULL6EN PULL5EN PULL4EN PULL3EN PULL2EN PULL1EN PULL0EN Write: Reset: 0 0 0 0 0 0 0 0 Read: Write: R R R R R R R R Read: UE0D07_OUT UE0D06_OUT UE0D05_OUT UE0D04_OUT UE0D03_OUT UE0D02_OUT UE0D01_OUT UE0D00_OUT Write: UE0D07_IN UE0D06_IN UE0D05_IN UE0D04_IN UE0D03_IN UE0D02_IN UE0D01_IN UE0D00_IN Reset: Unaffected by reset Read: UE0D17_OUT UE0D16_OUT UE0D15_OUT UE0D14_OUT UE0D13_OUT UE0D12_OUT UE0D11_OUT UE0D10_OUT Write: UE0D17_IN UE0D16_IN UE0D15_IN UE0D14_IN UE0D13_IN UE0D12_IN UE0D11_IN UE0D10_IN Reset: Unaffected by reset Read: UE0D27_OUT UE0D26_OUT UE0D25_OUT UE0D24_OUT UE0D23_OUT UE0D22_OUT UE0D21_OUT UE0D20_OUT Write: UE0D27_IN UE0D26_IN UE0D25_IN UE0D24_IN UE0D23_IN UE0D22_IN UE0D21_IN UE0D20_IN Reset: Unaffected by reset Read: UE0D37_OUT UE0D36_OUT UE0D35_OUT UE0D34_OUT UE0D33_OUT UE0D32_OUT UE0D31_OUT UE0D30_OUT Write: UE0D37_IN UE0D36_IN UE0D35_IN UE0D34_IN UE0D33_IN UE0D32_IN UE0D31_IN UE0D30_IN Reset: Unaffected by reset = Unimplemented R = Reserved U = Unaffected by reset Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 7) Freescale Semiconductor 29
Page 1: MC68HC908JW32 Data Sheet M68HC08 Mi
Page 4 and 5: The following revision history tabl
Page 6 and 7: List of Chapters MC68HC908JW32 Data
Page 8 and 9: Table of Contents Chapter 3 Configu
Page 10 and 11: Table of Contents 6.5.3 Reset . . .
Page 12 and 13: Table of Contents 10.12.1 MISO (Mas
Page 14 and 15: Table of Contents Chapter 16 Comput
Page 16 and 17: Table of Contents MC68HC908JW32 Dat
Page 18 and 19: General Description • External as
Page 20 and 21: General Description 1.5 Clock Tree
Page 22 and 23: General Description V DD V SS must
Page 24 and 25: General Description MC68HC908JW32 D
Page 26 and 27: Memory $0000 ↓ $005F $0060 ↓ $0
Page 30 and 31: Memory Addr. Register Name Bit 7 6
Page 32 and 33: Memory Addr. Register Name Bit 7 6
Page 34 and 35: Memory Table 2-1 is a list of vecto
Page 36 and 37: Memory 2.5.2 FLASH Control Register
Page 38 and 39: Memory This program sequence is rep
Page 40 and 41: Memory 2.5.7 FLASH Block Protect Re
Page 42 and 43: Configuration Registers (CONFIG) 3.
Page 44 and 45: Configuration Registers (CONFIG) MC
Page 46 and 47: Central Processor Unit (CPU) 15 15
Page 48 and 49: Central Processor Unit (CPU) 4.3.5
Page 50 and 51: Central Processor Unit (CPU) 4.7 In
Page 52 and 53: Central Processor Unit (CPU) Source
Page 54 and 55: Central Processor Unit (CPU) Source
Page 56 and 57: 56 Freescale Semiconductor MC68HC90
Page 58 and 59: Clock Generator Module (CGM) OSC2 O
Page 60 and 61: Clock Generator Module (CGM) 5.3.3
Page 62 and 63: Clock Generator Module (CGM) The fo
Page 64 and 65: Clock Generator Module (CGM) 9. Pro
Page 66 and 67: Clock Generator Module (CGM) 5.4 I/
Page 68 and 69: Clock Generator Module (CGM) BCS
Page 72 and 73: Clock Generator Module (CGM) VCO cl
Page 76 and 77: System Integration Module (SIM) RES
Page 78 and 79:
System Integration Module (SIM) 6.2
Page 80 and 81:
System Integration Module (SIM) At
Page 82 and 83:
System Integration Module (SIM) opt
Page 84 and 85:
System Integration Module (SIM) If
Page 86 and 87:
System Integration Module (SIM) Pri
Page 88 and 89:
System Integration Module (SIM) IAB
Page 90 and 91:
System Integration Module (SIM) 6.7
Page 92 and 93:
System Integration Module (SIM) MC6
Page 94 and 95:
Monitor Mode (MON) 1 µF 1 µF DB9
Page 96 and 97:
Monitor Mode (MON) Enter monitor mo
Page 98 and 99:
Monitor Mode (MON) FROM HOST ECHO R
Page 100 and 101:
Monitor Mode (MON) Table 7-7. IWRIT
Page 102 and 103:
Monitor Mode (MON) During monitor m
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Monitor Mode (MON) The control and
Page 106 and 107:
Monitor Mode (MON) The coding examp
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Timer Interface Module (TIM) 8.4 Fu
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Timer Interface Module (TIM) 8.4.3
Page 112 and 113:
Timer Interface Module (TIM) Use th
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Timer Interface Module (TIM) If TIM
Page 116 and 117:
Timer Interface Module (TIM) TRST
Page 118 and 119:
Timer Interface Module (TIM) Addres
Page 120 and 121:
Timer Interface Module (TIM) NOTE W
Page 122 and 123:
Timer Interface Module (TIM) MC68HC
Page 124 and 125:
Timebase Module (TBM) ÷ 2 ÷ 2 88-
Page 126 and 127:
Timebase Module (TBM) 9.6 Low-Power
Page 128 and 129:
Serial Peripheral Interface Module
Page 130 and 131:
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Page 148 and 149:
USB 2.0 FS Module 11.3 USB Module A
Page 150 and 151:
USB 2.0 FS Module 11.3.4 USB Reques
Page 152 and 153:
USB 2.0 FS Module There are 64-byte
Page 154 and 155:
USB 2.0 FS Module Addr. Register Na
Page 156 and 157:
USB 2.0 FS Module 11.5.2 USB Status
Page 158 and 159:
USB 2.0 FS Module USBRSTIE — USB
Page 160 and 161:
USB 2.0 FS Module SIZE[1:0] — Buf
Page 162 and 163:
USB 2.0 FS Module 11.5.8 USB Interf
Page 164 and 165:
PS2 Clock Generator (PS2CLK) CLK Ou
Page 166 and 167:
PS2 Clock Generator (PS2CLK) MC68HC
Page 168 and 169:
Input/Output (I/O) Ports Addr. Regi
Page 170 and 171:
Input/Output (I/O) Ports Port Bit D
Page 172 and 173:
Input/Output (I/O) Ports 13.3 Port
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Page 178 and 179:
Page 180 and 181:
Input/Output (I/O) Ports PTE3 pin f
Page 182 and 183:
Page 184 and 185:
Input/Output (I/O) Ports MC68HC908J
Page 186 and 187:
External Interrupt (IRQ) When set,
Page 188 and 189:
External Interrupt (IRQ) 14.5 PTE3/
Page 190 and 191:
External Interrupt (IRQ) MC68HC908J
Page 192 and 193:
Keyboard Interrupt Module (KBI) 15.
Page 194 and 195:
Keyboard Interrupt Module (KBI) 15.
Page 196 and 197:
Keyboard Interrupt Module (KBI) MC6
Page 198 and 199:
Computer Operating Properly (COP) T
Page 200 and 201:
Computer Operating Properly (COP) 1
Page 202 and 203:
Low-Voltage Inhibit (LVI) V DD LOW
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Low-Voltage Inhibit (LVI) MC68HC908
Page 206 and 207:
Break Module (BRK) 18.3 Functional
Page 208 and 209:
Break Module (BRK) BRKE — Break E
Page 210 and 211:
Break Module (BRK) MC68HC908JW32 Da
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Electrical Specifications 19.3 Func
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Electrical Specifications Pullup re
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Electrical Specifications 19.10 Tim
Page 218 and 219:
Electrical Specifications SS INPUT
Page 220 and 221:
Electrical Specifications MC68HC908
Page 232:
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MC68HC908JW32, MC68HC908JW32 - Data Sheet - Freescale

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