MC68HC908JW32, MC68HC908JW32 - Data Sheet - Freescale

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Memory $0000 ↓ $005F $0060 ↓ $045F $0460 ↓ $0FFF $1000 ↓ $103F $1040 ↓ $108F $1090 ↓ $1095 $1096 ↓ $6FFF $7000 ↓ $EFFF $F000 ↓ $F9FF $FA00 ↓ $FDFF I/O Registers 96 Bytes RAM 1,024 Bytes Unimplemented 2,976 Bytes USB Buffer RAM 64 Bytes Unimplemented 80 Bytes CGM Control Registers 6 bytes Unimplemented 24,426 FLASH 32,768 Bytes Unimplemented 3,559 Bytes Monitor ROM 1 1,024 Bytes $FE00 Break Status Register (BSR) $FE01 Reset Status Register (RSR) $FE02 Reserved $FE03 Break Flag Control Register (BFCR) $FE04 Interrupt Status Register 1 (INT1) $FE05 Interrupt Status Register 2 (INT2) $FE06 Interrupt Status Register 3 (INT3) $FE07 Reserved $FE08 FLASH Control Register (FLCR) $FE09 FLASH Block Protect Register (FLBPR) $FE0A Reserved $FE0B Reserved $FE0C Break Address High Register (BRKH) $FE0D Break Address Low Register (BRKL) $FE0E Break Status and Control Register (BRKSCR) $FE0F LVI Status Register (LVISR) $FE10 ↓ $FFCF $FFD0 ↓ $FFFF Monitor ROM 2 448 Bytes FLASH Vectors 48 Bytes Figure 2-1. Memory Map MC68HC908JW32 Data Sheet, Rev. 6 26 Freescale Semiconductor
MC68HC908JW32 Data Sheet, Rev. 6 Monitor ROM Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A Port A Data Register (PTA) Port B Data Register (PTB) Port C Data Register (PTC) Port D Data Register (PTD) Data Direction Register A (DDRA) Data Direction Register B (DDRB) Data Direction Register C (DDRC) Data Direction Register D (DDRD) Port E Data Register (PTE) Data Direction Register E (DDRE) Timer 1 Status and Control Register (T1SC) $000B Reserved $000C Timer 1 Counter Register High (T1CNTH) Read: Write: PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 Reset: Unaffected by reset Read: Write: PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 Reset: Unaffected by reset Read: Write: Reset: Unaffected by reset Read: Write: PTC3 PTC2 PTC1 PTC0 PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 Reset: Unaffected by reset Read: Write: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Reset: 0 0 0 0 0 0 0 0 Read: Write: DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 Reset: 0 0 0 0 0 0 0 0 Read: Write: DDRC3 DDRC2 DDRC1 DDRC0 Reset: 0 0 0 0 0 0 0 0 Read: Write: DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 Reset: 0 0 0 0 0 0 0 0 Read: Write: PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 Reset: Unaffected by reset Read: Write: DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 Reset: 0 0 0 0 0 0 0 0 Read: TOF 0 0 TOIE TSTOP Write: 0 TRST PS2 PS1 PS0 Reset: 0 0 1 0 0 0 0 0 Read: Write: R R R R R R R R Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented R = Reserved U = Unaffected by reset Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 7) Freescale Semiconductor 27
Page 1: MC68HC908JW32 Data Sheet M68HC08 Mi
Page 4 and 5: The following revision history tabl
Page 6 and 7: List of Chapters MC68HC908JW32 Data
Page 8 and 9: Table of Contents Chapter 3 Configu
Page 10 and 11: Table of Contents 6.5.3 Reset . . .
Page 12 and 13: Table of Contents 10.12.1 MISO (Mas
Page 14 and 15: Table of Contents Chapter 16 Comput
Page 16 and 17: Table of Contents MC68HC908JW32 Dat
Page 18 and 19: General Description • External as
Page 20 and 21: General Description 1.5 Clock Tree
Page 22 and 23: General Description V DD V SS must
Page 24 and 25: General Description MC68HC908JW32 D
Page 28 and 29: Memory Addr. Register Name Bit 7 6
Page 34 and 35: Memory Table 2-1 is a list of vecto
Page 36 and 37: Memory 2.5.2 FLASH Control Register
Page 38 and 39: Memory This program sequence is rep
Page 40 and 41: Memory 2.5.7 FLASH Block Protect Re
Page 42 and 43: Configuration Registers (CONFIG) 3.
Page 44 and 45: Configuration Registers (CONFIG) MC
Page 46 and 47: Central Processor Unit (CPU) 15 15
Page 48 and 49: Central Processor Unit (CPU) 4.3.5
Page 50 and 51: Central Processor Unit (CPU) 4.7 In
Page 52 and 53: Central Processor Unit (CPU) Source
Page 54 and 55: Central Processor Unit (CPU) Source
Page 56 and 57: 56 Freescale Semiconductor MC68HC90
Page 58 and 59: Clock Generator Module (CGM) OSC2 O
Page 60 and 61: Clock Generator Module (CGM) 5.3.3
Page 62 and 63: Clock Generator Module (CGM) The fo
Page 64 and 65: Clock Generator Module (CGM) 9. Pro
Page 66 and 67: Clock Generator Module (CGM) 5.4 I/
Page 68 and 69: Clock Generator Module (CGM) BCS
Page 72 and 73: Clock Generator Module (CGM) VCO cl
Page 76 and 77:
System Integration Module (SIM) RES
Page 78 and 79:
System Integration Module (SIM) 6.2
Page 80 and 81:
System Integration Module (SIM) At
Page 82 and 83:
System Integration Module (SIM) opt
Page 84 and 85:
System Integration Module (SIM) If
Page 86 and 87:
System Integration Module (SIM) Pri
Page 88 and 89:
System Integration Module (SIM) IAB
Page 90 and 91:
System Integration Module (SIM) 6.7
Page 92 and 93:
System Integration Module (SIM) MC6
Page 94 and 95:
Monitor Mode (MON) 1 µF 1 µF DB9
Page 96 and 97:
Monitor Mode (MON) Enter monitor mo
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Monitor Mode (MON) FROM HOST ECHO R
Page 100 and 101:
Monitor Mode (MON) Table 7-7. IWRIT
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Monitor Mode (MON) During monitor m
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Monitor Mode (MON) The control and
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Monitor Mode (MON) The coding examp
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Timer Interface Module (TIM) 8.4 Fu
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Timer Interface Module (TIM) 8.4.3
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Timer Interface Module (TIM) Use th
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Timer Interface Module (TIM) If TIM
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Timer Interface Module (TIM) TRST
Page 118 and 119:
Timer Interface Module (TIM) Addres
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Timer Interface Module (TIM) NOTE W
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Timer Interface Module (TIM) MC68HC
Page 124 and 125:
Timebase Module (TBM) ÷ 2 ÷ 2 88-
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Timebase Module (TBM) 9.6 Low-Power
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Serial Peripheral Interface Module
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USB 2.0 FS Module 11.3 USB Module A
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USB 2.0 FS Module 11.3.4 USB Reques
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USB 2.0 FS Module There are 64-byte
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USB 2.0 FS Module Addr. Register Na
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USB 2.0 FS Module 11.5.2 USB Status
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USB 2.0 FS Module USBRSTIE — USB
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USB 2.0 FS Module SIZE[1:0] — Buf
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USB 2.0 FS Module 11.5.8 USB Interf
Page 164 and 165:
PS2 Clock Generator (PS2CLK) CLK Ou
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PS2 Clock Generator (PS2CLK) MC68HC
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Input/Output (I/O) Ports Addr. Regi
Page 170 and 171:
Input/Output (I/O) Ports Port Bit D
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Input/Output (I/O) Ports 13.3 Port
Page 174 and 175:
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Input/Output (I/O) Ports PTE3 pin f
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Input/Output (I/O) Ports MC68HC908J
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External Interrupt (IRQ) When set,
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External Interrupt (IRQ) 14.5 PTE3/
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External Interrupt (IRQ) MC68HC908J
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Keyboard Interrupt Module (KBI) 15.
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Keyboard Interrupt Module (KBI) 15.
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Keyboard Interrupt Module (KBI) MC6
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Computer Operating Properly (COP) T
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Computer Operating Properly (COP) 1
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Low-Voltage Inhibit (LVI) V DD LOW
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Low-Voltage Inhibit (LVI) MC68HC908
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Break Module (BRK) 18.3 Functional
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Break Module (BRK) BRKE — Break E
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Break Module (BRK) MC68HC908JW32 Da
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Electrical Specifications 19.3 Func
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Electrical Specifications Pullup re
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Electrical Specifications 19.10 Tim
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Electrical Specifications SS INPUT
Page 220 and 221:
Electrical Specifications MC68HC908
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MC68HC908JW32, MC68HC908JW32 - Data Sheet - Freescale

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