MC68HC908JW32, MC68HC908JW32 - Data Sheet - Freescale

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Memory Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $005E $005F $1090 $1091 $1092 $1093 $1094 $1095 $FE00 USB EP 3/4 Base Pointer Register (UEP34BPR) USB Interface Control Register (UINTFCR) PLL Control Register (PTCL) PLL Bandwidth Control Register (PBWC) PLL Multiplier Select Register High (PMSH) PLL Multiplier Select Register Low (PMSL) PLL VCO Range Select Register (PMRS) PLL Reference Divider Select Register (PMDS) Break Status Register (BSR) Note: Writing a logic 0 clears SBSW. $FE01 Reset Status Register (RSR) $FE02 Reserved $FE03 Break Flag Control Register (BFCR) Read: Write: BASE42 BASE41 BASE40 BASE32 BASE31 BASE30 Reset: 0 0 0 0 0 0 0 0 Read: Write: EP4INT EP3INT EP2INT EP1INT Reset: 0 0 0 0 0 0 0 0 Read: Write: PLLIE PLLF MC68HC908JW32 Data Sheet, Rev. 6 PLLON BCS PRE1 PRE0 VPR1 VPR0 Reset: 0 0 1 0 0 0 0 0 Read: Write: AUTO LOCK 32 Freescale Semiconductor ACQ 0 0 0 0 Reset: 0 0 0 0 0 0 0 Read: 0 0 0 0 Write: MUL11 MUL10 MUL9 MUL8 Reset: 0 0 0 0 0 0 0 0 Read: Write: MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0 Reset: 0 1 0 0 0 0 0 0 Read: Write: VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0 Reset: 0 1 0 0 0 0 0 0 Read: 0 0 0 0 Write: RDS3 RDS2 RDS1 RDS0 Reset: 0 0 0 0 0 0 0 1 Read: SBSW R R R R R R Write: See note Reset: 0 Read: POR PIN COP ILOP ILAD USB LVI 0 Write: POR: 1 0 0 0 0 0 1 0 Read: Write: Read: Write: Reset: 0 R R R R R R R R BCFE R R R R R R R = Unimplemented R = Reserved U = Unaffected by reset Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 7) R R
MC68HC908JW32 Data Sheet, Rev. 6 Monitor ROM Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $FE04 $FE05 $FE06 Interrupt Status Register 1 (INT1) Interrupt Status Register 2 (INT2) Interrupt Status Register 3 (INT3) $FE07 Reserved $FE08 $FE09 FLASH Control Register (FLCR) FLASH Block Protect Register (FLBPR) $FE0A Reserved $FE0B Reserved $FE0C $FE0D $FE0E $FE0F $FFFF Break Address High Register (BRKH) Break Address low Register (BRKL) Break Status and Control Register (BRKSCR) LVI Sttatusl Register (LVISR) COP Control Register (COPCTL) Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 Read: 0 0 0 0 0 0 0 IF15 Write: R R R R R R R R Read: Write: 0 0 0 0 0 0 0 0 R R R R R R R R Read: 0 0 0 0 Write: HVEN MASS ERASE PGM Reset: 0 0 0 0 0 0 0 0 Read: Write: BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Reset: 0 0 0 0 0 0 0 0 Read: Write: Read: Write: Read: Write: R R R R R R R R R R R R R R R R Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Reset: 0 0 0 0 0 0 0 0 Read: Write: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset: 0 0 0 0 0 0 0 0 Read: Write: BRKE BRKA 0 0 0 0 0 0 Reset: 0 0 0 0 0 0 0 0 Read: LVIOUT 0 0 0 0 0 0 0 Write: Reset: 0 0 0 0 0 0 0 0 Read: Low byte of reset vector Write: Writing clears COP counter (any value) Reset: Unaffected by reset = Unimplemented R = Reserved U = Unaffected by reset Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 7) Freescale Semiconductor 33
Page 1: MC68HC908JW32 Data Sheet M68HC08 Mi
Page 4 and 5: The following revision history tabl
Page 6 and 7: List of Chapters MC68HC908JW32 Data
Page 8 and 9: Table of Contents Chapter 3 Configu
Page 10 and 11: Table of Contents 6.5.3 Reset . . .
Page 12 and 13: Table of Contents 10.12.1 MISO (Mas
Page 14 and 15: Table of Contents Chapter 16 Comput
Page 16 and 17: Table of Contents MC68HC908JW32 Dat
Page 18 and 19: General Description • External as
Page 20 and 21: General Description 1.5 Clock Tree
Page 22 and 23: General Description V DD V SS must
Page 24 and 25: General Description MC68HC908JW32 D
Page 26 and 27: Memory $0000 ↓ $005F $0060 ↓ $0
Page 28 and 29: Memory Addr. Register Name Bit 7 6
Page 30 and 31: Memory Addr. Register Name Bit 7 6
Page 34 and 35: Memory Table 2-1 is a list of vecto
Page 36 and 37: Memory 2.5.2 FLASH Control Register
Page 38 and 39: Memory This program sequence is rep
Page 40 and 41: Memory 2.5.7 FLASH Block Protect Re
Page 42 and 43: Configuration Registers (CONFIG) 3.
Page 44 and 45: Configuration Registers (CONFIG) MC
Page 46 and 47: Central Processor Unit (CPU) 15 15
Page 48 and 49: Central Processor Unit (CPU) 4.3.5
Page 50 and 51: Central Processor Unit (CPU) 4.7 In
Page 52 and 53: Central Processor Unit (CPU) Source
Page 54 and 55: Central Processor Unit (CPU) Source
Page 56 and 57: 56 Freescale Semiconductor MC68HC90
Page 58 and 59: Clock Generator Module (CGM) OSC2 O
Page 60 and 61: Clock Generator Module (CGM) 5.3.3
Page 62 and 63: Clock Generator Module (CGM) The fo
Page 64 and 65: Clock Generator Module (CGM) 9. Pro
Page 66 and 67: Clock Generator Module (CGM) 5.4 I/
Page 68 and 69: Clock Generator Module (CGM) BCS
Page 72 and 73: Clock Generator Module (CGM) VCO cl
Page 76 and 77: System Integration Module (SIM) RES
Page 78 and 79: System Integration Module (SIM) 6.2
Page 80 and 81: System Integration Module (SIM) At
Page 82 and 83:
System Integration Module (SIM) opt
Page 84 and 85:
System Integration Module (SIM) If
Page 86 and 87:
System Integration Module (SIM) Pri
Page 88 and 89:
System Integration Module (SIM) IAB
Page 90 and 91:
System Integration Module (SIM) 6.7
Page 92 and 93:
System Integration Module (SIM) MC6
Page 94 and 95:
Monitor Mode (MON) 1 µF 1 µF DB9
Page 96 and 97:
Monitor Mode (MON) Enter monitor mo
Page 98 and 99:
Monitor Mode (MON) FROM HOST ECHO R
Page 100 and 101:
Monitor Mode (MON) Table 7-7. IWRIT
Page 102 and 103:
Monitor Mode (MON) During monitor m
Page 104 and 105:
Monitor Mode (MON) The control and
Page 106 and 107:
Monitor Mode (MON) The coding examp
Page 108 and 109:
Timer Interface Module (TIM) 8.4 Fu
Page 110 and 111:
Timer Interface Module (TIM) 8.4.3
Page 112 and 113:
Timer Interface Module (TIM) Use th
Page 114 and 115:
Timer Interface Module (TIM) If TIM
Page 116 and 117:
Timer Interface Module (TIM) TRST
Page 118 and 119:
Timer Interface Module (TIM) Addres
Page 120 and 121:
Timer Interface Module (TIM) NOTE W
Page 122 and 123:
Timer Interface Module (TIM) MC68HC
Page 124 and 125:
Timebase Module (TBM) ÷ 2 ÷ 2 88-
Page 126 and 127:
Timebase Module (TBM) 9.6 Low-Power
Page 128 and 129:
Serial Peripheral Interface Module
Page 130 and 131:
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Page 148 and 149:
USB 2.0 FS Module 11.3 USB Module A
Page 150 and 151:
USB 2.0 FS Module 11.3.4 USB Reques
Page 152 and 153:
USB 2.0 FS Module There are 64-byte
Page 154 and 155:
USB 2.0 FS Module Addr. Register Na
Page 156 and 157:
USB 2.0 FS Module 11.5.2 USB Status
Page 158 and 159:
USB 2.0 FS Module USBRSTIE — USB
Page 160 and 161:
USB 2.0 FS Module SIZE[1:0] — Buf
Page 162 and 163:
USB 2.0 FS Module 11.5.8 USB Interf
Page 164 and 165:
PS2 Clock Generator (PS2CLK) CLK Ou
Page 166 and 167:
PS2 Clock Generator (PS2CLK) MC68HC
Page 168 and 169:
Input/Output (I/O) Ports Addr. Regi
Page 170 and 171:
Input/Output (I/O) Ports Port Bit D
Page 172 and 173:
Input/Output (I/O) Ports 13.3 Port
Page 174 and 175:
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Page 178 and 179:
Page 180 and 181:
Input/Output (I/O) Ports PTE3 pin f
Page 182 and 183:
Page 184 and 185:
Input/Output (I/O) Ports MC68HC908J
Page 186 and 187:
External Interrupt (IRQ) When set,
Page 188 and 189:
External Interrupt (IRQ) 14.5 PTE3/
Page 190 and 191:
External Interrupt (IRQ) MC68HC908J
Page 192 and 193:
Keyboard Interrupt Module (KBI) 15.
Page 194 and 195:
Keyboard Interrupt Module (KBI) 15.
Page 196 and 197:
Keyboard Interrupt Module (KBI) MC6
Page 198 and 199:
Computer Operating Properly (COP) T
Page 200 and 201:
Computer Operating Properly (COP) 1
Page 202 and 203:
Low-Voltage Inhibit (LVI) V DD LOW
Page 204 and 205:
Low-Voltage Inhibit (LVI) MC68HC908
Page 206 and 207:
Break Module (BRK) 18.3 Functional
Page 208 and 209:
Break Module (BRK) BRKE — Break E
Page 210 and 211:
Break Module (BRK) MC68HC908JW32 Da
Page 212 and 213:
Electrical Specifications 19.3 Func
Page 214 and 215:
Electrical Specifications Pullup re
Page 216 and 217:
Electrical Specifications 19.10 Tim
Page 218 and 219:
Electrical Specifications SS INPUT
Page 220 and 221:
Electrical Specifications MC68HC908
Page 232:
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