On-chip Networks for Manycore Architecture Myong ... - People - MIT

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deadlock-free, fine-grained thread migration protocol. This research not only solves the specific problem of e cient cycle-level thread migration, but also encourages a design paradigm that relaxes the conventional abstraction and uses the resources of the network to support higher-level functionality. Finally, we have undertaken the arduous task of implementing a 110-core EM 2 processor on silicon. This e↵ort has helped to address realistic implementation constraints and provided perspective for future research. An important lesson that can be learned from this thesis is that, an on-chip network is not just about making physical connections between system components. The benefits and constraints that each component brings to the system are consolidated into a complex global design space by an on-chip network. Therefore, the on-chip network must take a role as an arbiter and tightly integrate the components to meet the design goals. For example, ENC is designed to take the burden of deadlock prevention o↵ processor cores; shipping the context of a running thread out of the pipeline is an essential operation to solve the deadlock issue because it forces progress. In order to not lose the thread context, however, the evicted thread must be stored in another place immediately. And because the registers in processor cores are tightly utilized, it is better to store the context in a relatively underutilized resource – the network bu↵er. Therefore, ENC puts only the minimum amount of additional bu↵er in processor cores (for just one thread context at its native core), and lets the thread context utilize the ample network bu↵er until it arrives at its native core. This is a example of resource arbitration between system components, which is e ciently handled by the on-chip network. Future on-chip network design for manycore architecture must take this role into account and take charge in orchestrating all system components. 108
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On-chip Networks for Manycore Archi
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Acknowledgments This thesis would n
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Contents 1 Introduction 15 1.1 Chip
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4.2.2 Evaluation with Synthetic Mig
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3-11 BAN performance under bursty t
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Chapter 1 Introduction 1.1 Chip Mul
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However, a simple common bus is not
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Name #Cores Technology Frequency Po
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1.2.3 System-Level Optimization Whi
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gestion dynamically, it may have lo
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2-phase n-phase DOR O1TURN Valiant
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B 1 1 D 0.5 A 0.5 0.5 S 0.5 Figure
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instanceproma x instancepromb D x D
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(a) West-First (rotated 180 ) (b) N
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proof allocvc D4 D1 D4 D1 S m/2+1:m
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2.4 Experimental Results To evaluat
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Characteristic Configuration Topolo
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Using Exclusive Dynamic VC allocati
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2.2 Bit-complement 2.4 Bit-reverse
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Chapter 3 Oblivious Routing in On-c
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andwidth of the link in one directi
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3.2.2 Bidirectional Links In the co
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neighbor mesh network. As can be se
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ectional links. Consequently, the r
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approach: the arbiter makes its dec
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Page 114 and 115: [63] Gordon E. Moore. Cramming more
Page 116: [88] Sriram Vangal, Nitin Borkar, a
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