On-chip Networks for Manycore Architecture Myong ... - People - MIT

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Chapter 2 Oblivious Routing with Path Diversity 2.1 Introduction The early part of this thesis focuses on network-level optimization techniques. These techniques abstract the on-chip network from other system components and aim to improve the performance of the network under general tra c patterns. In this approach, the choice of routing algorithm is a particularly important matter since routing is one of the key factors that determines the performance of a network [18]. This chapter will discuss oblivious routing schemes for on-chip networks, present a solution, Path-based, Randomized, Oblivious, Minimal (PROM) routing [10], and show how it improves the diversity of routes and provides better throughput across a class of tra c patterns. 2.1.1 Oblivious vs. Adaptive Routing Routing algorithms can be classified into two categories: oblivious and adaptive. Oblivious routing algorithms choose a route without regard to the state of the network. Adaptive algorithms, on the other hand, determine what path a packet takes based on network congestion. Because oblivious routing cannot avoid network con- 23
Page 1: On-chip Networks for Manycore Archi
Page 5 and 6: Acknowledgments This thesis would n
Page 7 and 8: Contents 1 Introduction 15 1.1 Chip
Page 9: 4.2.2 Evaluation with Synthetic Mig
Page 12 and 13: 3-11 BAN performance under bursty t
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Page 17 and 18: However, a simple common bus is not
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Page 25 and 26: minimum number of hops, a feature k
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Page 33 and 34: to both turn models. Once the sourc
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Page 37 and 38: Name Pattern Example (b=4) Bit-comp
Page 39 and 40: under this allocation scheme multip
Page 41 and 42: to O1TURN and simpler than 2-phase
Page 43: 2.2 Bit-complement 2.4 Bit-reverse
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Page 48 and 49: (1,…,p) RoutingLogic VirtualChann
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the case where each core has a cont
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Figure 4-4: The percentage of acces
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grate on their own because, for exa
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4.4 Performance Evaluation 4.4.1 Ba
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network-independent traces (NITs) f
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Figure 4-5: Total migration cost of
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Figure 4-6: Total migration distanc
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Figure 4-8: Total migration cost of
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Chapter 5 Physical Implementation o
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accesses while it stays at the dest
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600 I/O pins, while flip chip can p
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(a) (b) Figure 5-2: EM 2 tile floor
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Figure 5-4: EM 2 tile layout that o
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Figure 5-5: EM 2 chip-level floorpl
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(a) Tile-level (b) Chip-level Figur
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(a) Tile-level view (b) Inside the
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of migration tra c. If we cannot si
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Chapter 6 Conclusions 6.1 Thesis Co
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Bibliography [1] Arvind, Nirav Dave
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[25] Hadi Esmaeilzadeh, Emily Blem,
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[51] Kangmin Lee, Se-Joong Lee, and
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[75] S. Rusu, Simon Tam, H. Muljono
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