On-chip Networks for Manycore Architecture Myong ... - People - MIT

work to support specific mechanisms. For instance, directory-based cache coherence
protocols require frequent multicast or broadcast, which is a challenge for the on-chip
network to implement e ciently.
Researchers have taken many di↵erent approaches to on-chip networks to overcome
the challenges of manycore architecture. These approaches can be categorized into
circuit-level optimization, network-level optimization, and system-level optimization.
1.2.1 Circuit-level Optimization
Research in this category aims at improving the performance and reducing the cost of
data movement through better circuit design. For example, a double-pumped crossbar
channel with a location-based channel driver (LBD), which reduces the crossbar
hardware cost by half [88], was used in the mesh interconnect of the Intel manycore
processor [37]. The ring interconnect used for the Intel Nehalem-EX Xeon microprocessor
also exploits circuit-level techniques such as conditional clocking, fully shielded
wire routing, etc., to optimize its design [68]. Self-resetting logic repeaters (SRLR) is
another example that incorporates circuit techniques to better explore the trade-o↵
between area, power, and performance [69].
1.2.2 Network-level Optimization
The logical and architectural design of the on-chip network plays an essential role in
both the functionality and performance of the on-chip network. An extensive range of
network topologies have been proposed and examined over the years [18]. Routing [87,
65, 66, 76, 49, 31, 9] is another key factor that determines the characteristics of onchip
communication. This level of optimization also has a significant impact on the
power dissipation of the network because the amount of energy consumed by onchip
network is directly related to activity on the network. Therefore, using better
communication schemes can result in reducing the power usage as shown in [51].
20