On-chip Networks for Manycore Architecture Myong ... - People - MIT

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(1,…,p) RoutingLogic VirtualChannelAllocator SwitchAllocator Creditsinin Flitsinin (1,…,v) Creditsout 1 tovDE EMUX (1,…,v) vto1M MUX pbyp p crossbar switch Flitsout (1,…,p) Figure 3-1: Conventional router architecture with p physical channels and v virtual channels per physical channel. as if there were multiple “virtual” channels. When a flit is ready to move, the switch connects an input bu↵er to an appropriate output channel. To control the datapath, the router also contains three major control modules: a router, a virtual-channel (VC) allocator, and a switch allocator. These control modules determine the next hop, the next virtual channel, and when a switch is available for each packet/flit. Routing comprises four steps: routing (RC), virtual-channel allocation (VA), switch allocation (SA), and switch traversal (ST); these are often implemented as four pipeline stages in modern virtual-channel routers. When a head flit (the first flit of a packet) arrives at an input channel, the router stores the flit in the bu↵er for the allocated virtual channel and determines the next hop node for the packet (RC stage). Given the next hop, the router then allocates a virtual channel in the next hop (VA stage). The next hop node and virtual channel decision is then used for the remaining flits of the given packet, and the relevant virtual channel is exclusively allocated to that packet until the packet transmission completes. Finally, if the next hop can accept the flit, the flit competes for a switch (SA stage), and moves to the output port (ST stage). 48
3.2.2 Bidirectional Links In the conventional virtual-channel router shown in Figure 3-1, each output channel is connected to an input bu↵er in an adjacent router by a unidirectional link; the maximum bandwidth is related to the number of physical wires that constitute the link. In an on-chip 2-D mesh with nearest neighbor connections there will always be two links in close proximity to each other, delivering packets in opposite directions. We propose to merge the two links between a pair of network nodes into a set of bidirectional links, each of which can be configured to deliver packets in either direction, increasing the bandwidth in one direction at the expense of the other. The links can be driven from two di↵erent sources, with local arbitration logic and tristate bu↵ers ensuring that both do not simultaneously drive the same wire. A A B B (a)FlowAisdominant (b)FlowBisdominant Figure 3-2: Adaptivity of a mesh network with bidirectional links Figure 3-2 illustrates the adaptivity of a mesh network using bidirectional links. Flow A is generated at the upper left corner and goes to the bottom right corner, while flow B is generated at the bottom left corner and ends at the upper right corner. When one flow becomes dominant, bidirectional links change their directions in order to achieve maximal total throughput. In this way, the network capacity for each flow can be adjusted taking into account flow burstiness without changing routes. Figure 3-3 shows a bidirectional link connecting two network nodes (for clarity, 49
Page 1: On-chip Networks for Manycore Archi
Page 5 and 6: Acknowledgments This thesis would n
Page 7 and 8: Contents 1 Introduction 15 1.1 Chip
Page 9: 4.2.2 Evaluation with Synthetic Mig
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Page 15 and 16: Chapter 1 Introduction 1.1 Chip Mul
Page 17 and 18: However, a simple common bus is not
Page 19 and 20: Name #Cores Technology Frequency Po
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Page 24 and 25: gestion dynamically, it may have lo
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Page 28 and 29: B 1 1 D 0.5 A 0.5 0.5 S 0.5 Figure
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Page 38 and 39: Characteristic Configuration Topolo
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Page 42 and 43: 2.2 Bit-complement 2.4 Bit-reverse
Page 45 and 46: Chapter 3 Oblivious Routing in On-c
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Page 53 and 54: ectional links. Consequently, the r
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locks. Figure 5-3 illustrates the a
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(a) A corner of global power rings
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Figure 5-9: Tapeout-ready EM 2 proc
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(a) Concentrate-in Figure 5-11: Mig
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deadlock-free, fine-grained thread
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[12] Intel Corporation. Intel deliv
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[38] Jason Howard, Saurabh Dighe, Y
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[63] Gordon E. Moore. Cramming more
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[88] Sriram Vangal, Nitin Borkar, a
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