On-chip Networks for Manycore Architecture Myong ... - People - MIT

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Characteristic Configuration Topology 8x8 2D MESH Link configuration (u, b) = (1,0), (0,2) (2,0), (1,2), (0,4) Routing DOR-XY and DOR-YX VC output multiplexing None, Matching maximum bandwidth Per-hop latency 1 cycle Virtual channels per port 4 Flit bu↵ers per VC 4 Average packet length (flits) 8 Tra c workload transpose, bit-complement, shu✏e, uniform-random profiled H.264 decoder Burstiness model Markov modulated process Warmup cycles 20,000 Analyzed cycles 100,000 Table 3.2: Simulation details for BAN and unidirectional networks of bandwidth allocation to estimate the impact on architectures where a dead cycle is required to switch the link direction. Although the bidirectional routing technique applies to various oblivious routing algorithms, we have, for evaluation purposes, focused on Dimension Ordered Routing (DOR), the most widely implemented oblivious routing method. While our experiments included both DOR-XY and DOR-YX routing, we did not see significant di↵erences in the results, and consequently report only DOR-XY results. In all of our experiments, the router was configured for four virtual channels per ingress port under a dynamic virtual channel allocation regimen. The e↵ect of multiplexing virtual channels in front of the crossbar switches was also examined. 3.4.2 Non-bursty Synthetic Tra c Figure 3-7 shows the throughput in the unidirectional and bidirectional networks under non-bursty tra c. When tra c is consistent, the improvement o↵ered by bidirectional links depends on how symmetric the flows are. On the one extreme, bit-complement, which in steady state is entirely symmetric when routed using DOR 58
Total Throughput (packets/cycle) 7 6 5 4 3 2 Transpose U=1,B=0 U=0,B=2 U=2,B=0 U=1,B=2 U=0,B=4 Total Throughput (packets/cycle) 9 8 7 6 5 4 3 2 U=1,B=0 U=0,B=2 U=2,B=0 U=1,B=2 U=0,B=4 Shuffle 1 0 10 20 30 40 50 60 Offered Injection Rate (packets/cycle) 1 0 10 20 30 40 50 60 70 Offered Injection Rate (packets/cycle) Total Throughput (packets/cycle) 4 3.5 3 2.5 2 1.5 1 Bitcomp U=1,B=0 U=0,B=2 U=2,B=0 U=1,B=2 U=0,B=4 Total Throughput (packets/cycle) 8 7 6 5 4 3 2 Uniform Random U=1,B=0 U=0,B=2 U=2,B=0 U=1,B=2 U=0,B=4 0.5 0 10 20 30 40 50 60 70 Offered Injection Rate (packets/cycle) 1 0 10 20 30 40 50 60 70 Offered Injection Rate (packets/cycle) Total Throughput (packets/cycle) 7 6 5 4 3 Transpose with Multiplexing U=1,B=0 U=0,B=2 U=2,B=0 U=1,B=2 U=0,B=4 Total Throughput (packets/cycle) 9 8 7 6 5 4 3 U=1,B=0 U=0,B=2 U=2,B=0 U=1,B=2 U=0,B=4 Shuffle with Multiplexing 2 2 1 0 10 20 30 40 50 60 Offered Injection Rate (packets/cycle) 1 0 10 20 30 40 50 60 70 Offered Injection Rate (packets/cycle) Total Throughput (packets/cycle) 4 3.5 3 2.5 2 1.5 Bitcomp with Multiplexing U=1,B=0 U=0,B=2 U=2,B=0 U=1,B=2 U=0,B=4 Total Throughput (packets/cycle) 8 7 6 5 4 3 Uniform Random with Multiplexing U=1,B=0 U=0,B=2 U=2,B=0 U=1,B=2 U=0,B=4 1 2 0.5 0 10 20 30 40 50 60 70 Offered Injection Rate (packets/cycle) 1 0 10 20 30 40 50 60 70 Offered Injection Rate (packets/cycle) Figure 3-7: Throughput of BAN and unidirectional networks under non-bursty tra c 59
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On-chip Networks for Manycore Archi
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Acknowledgments This thesis would n
Page 7 and 8: Contents 1 Introduction 15 1.1 Chip
Page 9: 4.2.2 Evaluation with Synthetic Mig
Page 12 and 13: 3-11 BAN performance under bursty t
Page 15 and 16: Chapter 1 Introduction 1.1 Chip Mul
Page 17 and 18: However, a simple common bus is not
Page 19 and 20: Name #Cores Technology Frequency Po
Page 21: 1.2.3 System-Level Optimization Whi
Page 24 and 25: gestion dynamically, it may have lo
Page 26 and 27: 2-phase n-phase DOR O1TURN Valiant
Page 28 and 29: B 1 1 D 0.5 A 0.5 0.5 S 0.5 Figure
Page 30 and 31: instanceproma x instancepromb D x D
Page 32 and 33: (a) West-First (rotated 180 ) (b) N
Page 34 and 35: proof allocvc D4 D1 D4 D1 S m/2+1:m
Page 36 and 37: 2.4 Experimental Results To evaluat
Page 38 and 39: Characteristic Configuration Topolo
Page 40 and 41: Using Exclusive Dynamic VC allocati
Page 42 and 43: 2.2 Bit-complement 2.4 Bit-reverse
Page 45 and 46: Chapter 3 Oblivious Routing in On-c
Page 47 and 48: andwidth of the link in one directi
Page 49 and 50: 3.2.2 Bidirectional Links In the co
Page 51 and 52: neighbor mesh network. As can be se
Page 53 and 54: ectional links. Consequently, the r
Page 55 and 56: approach: the arbiter makes its dec
Page 57: 3.4 Results and Comparisons 3.4.1 E
Page 61 and 62: 3.4.3 Non-bursty Synthetic Tra c wi
Page 63 and 64: Total Throughput (packets/cycle) 6
Page 65: from asymmetric bandwidth allocatio
Page 68 and 69: and is performed by the operating s
Page 70 and 71: a core can block contexts arriving
Page 72 and 73: Figure 4-2: Deadlock scenarios with
Page 74 and 75: N n →C n This node depends on not
Page 76 and 77: 4.3.1 The Basic ENC Algorithm (ENC0
Page 78 and 79: advance to the next cycle. This alg
Page 80 and 81: 4.4.2 Network-Independent Traces (N
Page 82 and 83: Protocols and Migration Patterns Mi
Page 84 and 85: RANDOM FFT RADIX LU OCEAN WATER 8 6
Page 86 and 87: Figure 4-7: Part of migration cost
Page 88 and 89: and where to migrate; a thread may
Page 90 and 91: 32KB D$ 8KB I$ Core Predictor Route
Page 92 and 93: instructions follow a custom stack-
Page 94 and 95: compromised performance for power e
Page 96 and 97: (a) Processor core (b) Migration pr
Page 98 and 99: locks. Figure 5-3 illustrates the a
Page 100 and 101: (a) A corner of global power rings
Page 102 and 103: Figure 5-9: Tapeout-ready EM 2 proc
Page 104 and 105: (a) Concentrate-in Figure 5-11: Mig
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deadlock-free, fine-grained thread
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[12] Intel Corporation. Intel deliv
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[38] Jason Howard, Saurabh Dighe, Y
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[63] Gordon E. Moore. Cramming more
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[88] Sriram Vangal, Nitin Borkar, a
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