On-chip Networks for Manycore Architecture Myong ... - People - MIT

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gestion dynamically, it may have lower worst-case and average-case throughput than adaptive routing. However, its low-complexity implementation often outweighs any potential loss in performance because an on-chip network is usually designed within tight power and area budgets [43]. Although many researchers have proposed cost-e↵ective adaptive routing algorithms [3, 16, 26, 31, 33, 40, 48, 84], this chapter focuses on oblivious routing for the following reasons. First, adaptive routing improves the performance only if the network has considerable amount of congestion; on the other hand, when congestion is low oblivious routing performs better than adaptive routing due to the extra logic required by adaptive routing. Because an on-chip network usually provides ample bandwidth relative to demand, it is not easy to justify the implementation cost of adaptive routing. Furthermore, the cost of adaptive routing is more severe for an on-chip network than for its large-scale counterparts. Many large-scale data networks, such as a wireless network, have unreliable nodes and links. Therefore, it is important for every node to report its status to other nodes so each node can keep track of ever-changing network topology. Because the network nodes are already sharing the network status, adaptive routing can exploit this knowledge to make better routing decisions without additional costs. In contrast, on-chip networks have extremely reliable links among the network nodes so they do not require constant status checking amongst the nodes. Therefore, monitoring the network status for adaptive routing always incurs extra costs in on-chip networks. 2.1.2 Deterministic vs. Path-diverse Oblivious Routing Deterministic routing is a subset of oblivious routing, which always chooses the same route between the same source-destination pair. Deterministic routing algorithms are widely used in on-chip network designs due to their low-complexity implementation. Dimension-ordered routing (DOR) is an extremely simple routing algorithm for a broad class of networks that include 2D mesh networks [17]. Packets simply route along one dimension first and then in the next dimension, and no path exceeds the 24
minimum number of hops, a feature known as “minimal routing”. Although it enables low-complexity implementation, the simplicity comes at the cost of poor worst-case and average-case throughput for mesh networks 1 . Path-diverse oblivious routing algorithms attempt to balance channel load by randomly selecting paths between sources and their respective destinations. Valiant [87] algorithm routes each packet via a random intermediate node. Whenever a packet is injected, the source node randomly chooses an intermediate node for the packet anywhere in the network; the packet then first travels toward the intermediate node using DOR, and, after reaching the intermediate node, continues to the original destination node, also using DOR. Although the Valiant algorithm has provably optimal worst-case throughput, its low average-case throughput and high latency have prevented widespread adoption. ROMM [65, 66] also routes packets through intermediate nodes, but it reduces latency by confining the intermediate nodes to the minimal routing region. n-phase ROMM is a variant of ROMM that uses n The 1 di↵erent intermediate nodes that divide each route into n di↵erent phases so as to increase path diversity. Although ROMM outperforms DOR in many cases, the worst-case performance of the most popular (2-phase) variant on 2D meshes and tori has been shown to be significantly worse than optimal [85, 76], and the overhead of n-phase ROMM has hindered real-world use. O1TURN [76] on a 2D mesh selects one of the DOR routes (XY or YX) uniformly at random, and o↵ers performance roughly equivalent to 2-phase ROMM over standard benchmarks combined with near-optimal worst-case throughput; however, its limited path diversity limits performance on some tra c patterns. Unlike DOR, each path-diverse algorithm may create dependency cycles amongst its routes, so it requires extra hardware to break those cycles and prevent network- 1 The worst-case throughput of a routing algorithm on a network is defined as the minimum throughput over all tra c patterns. The average-case throughput is its average throughput over all tra c patterns. Methods have been given to compute worst-case throughput [85] and approximate average-case throughput by using a finite set of random tra c patterns [86]. While these models of worst-case and average-case throughput are important from a theoretical standpoint, they do not model aspects such as head-of-line blocking, and our primary focus here is evaluating performance on a set of benchmarks that have a variety of local and non-local bursty tra c. 25
Page 1: On-chip Networks for Manycore Archi
Page 5 and 6: Acknowledgments This thesis would n
Page 7 and 8: Contents 1 Introduction 15 1.1 Chip
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Page 17 and 18: However, a simple common bus is not
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Page 40 and 41: Using Exclusive Dynamic VC allocati
Page 42 and 43: 2.2 Bit-complement 2.4 Bit-reverse
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Page 47 and 48: andwidth of the link in one directi
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N n →C n This node depends on not
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4.3.1 The Basic ENC Algorithm (ENC0
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advance to the next cycle. This alg
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4.4.2 Network-Independent Traces (N
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Protocols and Migration Patterns Mi
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RANDOM FFT RADIX LU OCEAN WATER 8 6
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Figure 4-7: Part of migration cost
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and where to migrate; a thread may
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32KB D$ 8KB I$ Core Predictor Route
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instructions follow a custom stack-
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compromised performance for power e
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(a) Processor core (b) Migration pr
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locks. Figure 5-3 illustrates the a
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(a) A corner of global power rings
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Figure 5-9: Tapeout-ready EM 2 proc
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(a) Concentrate-in Figure 5-11: Mig
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deadlock-free, fine-grained thread
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[12] Intel Corporation. Intel deliv
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[38] Jason Howard, Saurabh Dighe, Y
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[63] Gordon E. Moore. Cramming more
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[88] Sriram Vangal, Nitin Borkar, a
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