Spectral Estimation Using a MUSIC Algorithm - Altera

Spectral Estimation Using a MUSIC Algorithm
Figure 9. RTL of Complex CORDIC
vec_rot
clk
reset
R_x_real_in[21:0]
[21:0]
reg_gen_enZ2
reset
clk
1 ro[0]
clk_en
1
reg_gen_enZ2
reset
clk
clk_en
ri[0]
ro[0]
reg_gen_enZ1
reset
clk
ro[17:0]
clk_en
[17:0]
ri[17:0]
[17:0]
1
[21:0]
[21:0]
[17:0]
start
[21:0]
clk_en x_out[21:0]
xout_real_th[21:0]
[21:0]
output_en
[21:0]
y_out[21:0]
vec_rot_sel
[21:0]
result[17:0]
dataa[21:0]
[17:0]
datab[21:0]
zin[17:0]
vec_rot_theta_real
ri[0]
vec_rot_sel_delay2
theta_real_store
reset
reg_gen_enZ2
reset
vec_rot_sel_reg1
clk
output_en
1
clk
clk_en
ri[0]
ro[0]
vec_rot
clk
reset
vec_rot
output_delay
[21:0]
xin_imag[21:0]
start
xin_real[21:0]
[21:0]
reg_gen_enZ2
reset
clk
1
clk_en
ro[0]
vec_rot_sel
ri[0]
[17:0]
1
[21:0]
reg_gen_enZ1
reset
[21:0]
clk
[17:0]
ro[17:0]
clk_en
[17:0]
ri[17:0]
clk
reset
start
[21:0]
clk_en x_out[21:0]
output_en
y_out[21:0]
vec_rot_sel
[21:0]
result[17:0]
dataa[21:0]
datab[21:0]
zin[17:0]
vec_rot_inst
mux_genZ3
sel
mux_out[21:0]
[21:0]
A[21:0]
[21:0]
B[21:0]
mux_vec
start
1 [21:0]
[21:0] clk_en x_out[21:0]
xout_imag_th[21:0]
[21:0]
output_en
y_out[21:0]
[21:0]
xout_imag_th_next[21:0]
vec_rot_sel
[21:0]
[21:0]
result[17:0]
dataa[21:0]
[17:0]
[21:0]
datab[21:0]
[17:0]
zin[17:0]
vec_rot_theta_imag
vec_rot_sel_delay1
phi_store
reg_gen_enZ1
R_x_imag_in[21:0]
[21:0]
[17:0]
reset
clk
clk_en
ri[17:0]
ro[17:0]
[17:0]
theta_imag_store
This complex CORDIC block is the key block for EVD. It comprises three CORDIC blocks and one
phi-CORDIC block. These blocks are used for compensating the imaginary part of the complex input,
the two theta-CORDIC ones are for the real part and the other is for the imaginary part. Because we are
using a complex CORDIC in a time division multiplex manner, the angles phi and theta are stored in
vector mode and these angles are used subsequently in rotation mode. The output block is important, as
shown in Figure 10, for storing the final result and generating the control-signal-like interrupt when
EVD is over. It also provides all necessary addresses and bus control signals for interfacing with the
Nios II processor.
Figure 10. Output Block
load_en
reset
done
clk
cordic_clock
1
address_wr_op
reset
tc
clk
address[5:0]
clk_en
[5:0]
1
reg_gen_enZ4
reset
clk
ro[0]
clk_en
ri[0]
tc_reg_1
address_wr_op
reset
[5:0]
tc
clk
[5:0]
address[5:0]
1
clk_en
address_wirte_inst
[5:0]
mux_rd_wr_address_inst
sel
mux_genZ2
[5:0]
A[5:0]
[5:0]
mux_out[5:0]
B[5:0]
address_rd_wr[5:0]
address_read_inst
[5:0]
rd_wr
address_rd[5:0]
81