Main Memory Technology Direction - Micron

Main Memory Technology
Direction
Kevin Kilbuck
Senior Segment Marketing Manager
Computing and Servers
Micron Technology, Inc.
©2007 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products
and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Dates are estimates
only. Drawings not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective
owners.

Agenda
DRAM Technology Trends
Computing Customer Requirements
Introduction to DDR3

DRAM Technology
Trends

Main Memory Data Rate Trends
Data Rate (MT/s)
7000
6000
5000
4000
3000
2000
1000
0
SDRAM
DDR
DDR2
1995 2000 2005 2010
Year
• DRAM bandwidth requirements typically double
every three years
NGM Diff
NGM SE
DDR3

Unit Interval (Bit-Time) (Bit Time) Trends
Unit Interval (ps)
100000
10000
1000
100
SDRAM
DDR
DDR2
• 30–40% of UI will be budgeted for RX circuits
(jitter + S/H + static)
DDR3
NGM Diff
1995 2000 2005 2010
Year
625ps
NGM SE 313ps
156ps

Die Size Impact
Die Size
100
90
80
70
60
50
40
Die Size vs. Technology
115nm 95nm 78nm
Process Node
Triple Metal
DDR
DDR2
DDR3
GDDR4

IDD DD Impact IDD vs. Technology
Idd (mA)
2500
2000
1500
1000
500
0
400 Mb/s
800 Mb/s
DDR DDR2 DDR3 GDDR3 GDDR4
X16
1.33 Gb/s
1.6 Gb/s
X32
2.5 Gb/s
IDD4R
IDD4W
IDD7

Power Dissipation Trends
Power
900.0E-03
800.0E-03
700.0E-03
600.0E-03
500.0E-03
400.0E-03
300.0E-03
200.0E-03
100.0E-03
000.0E+00
256Mb SDRAM512Mb
DDR 1Gb DDR2 333
167 MHz 200 Mhz MHz
• x16 devices at nominal VDD
Technology
1Gb DDR3
1333 MHz
30.0E-03
25.0E-03
20.0E-03
15.0E-03
10.0E-03
5.0E-03
000.0E+00
P_IDD4
P_IDD2
Linear (P_IDD2)
Linear (P_IDD4)

Voltage Scaling
7
6
5
4
3
2
1
0
1990 1995 2000 2005 2010
Historical
Enthusiast

Historical DRAM Price-Per Price Per-Bit Bit
Decline ~35%/year
Price per Bit ( (Millicents Millicents)
1
1979
1981
1980
1982
1983
1985
Historical
price-per price per-bit bit decline has
averaged 35.5%
(1978–2002)
(1978 2002)
100
1984
1986
1987
1988
DRAM Market Price-per Price per-bit bit Decline
(Normalized- (Normalized Millicent/bit)
1989
1990
1991 1992
1993
10,000
1994
1995
1996
1998
Cumulative Bit Volume (10 12 )
1997
1999
2001
2000
2002
1,000,000
2003
2005F
2004F
2006F
2007F
2008F
100,000,000

Industry Analyst DRAM
Interface Forecast
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
2005 2006 2007 2008 2009 2010 2011
Source: IDC, Isuppli, Gartner, Micron Q107
2Gb
1Gb
512Mb
256Mb
128Mb
64Mb

Industry Analyst DRAM
Interface Forecast
100%
80%
60%
40%
20%
0%
Source: IDC, iSuppli Q107
DDR3 becomes
mainstream in 2009
2005 2006 2007 2008 2009 2010 2011
DDR3
DDR2
DDR
SDRAM

Computing Customer
Requirements

You Can’t Can t Have It All
Quality
Cost Power
DRAM Design &
Process Constraints
Density Bandwidth Latency
Pick two (maybe three if you’re you re really
lucky!)

What Computing
Customers Care About
What is Most Important?
Mobile/Laptop Desktop Server
Quality
Cost
Power
Bandwidth
Density
Latency

What Computing
Customers Care About
7
6
5
4
3
2
1
0
What is Most Important?
Quality Cost Power Bandwidth Density Latency
Mobile/Laptop
Desktop
Server

Microsoft’s Microsoft s Vista System
Requirements
CPU
Minimum
Minimum Recommended by SKU
Supported Home Basic All Other SKUs
An 800 MHz x86 or x64
processor 3
A 1 GHz x86 or x64 processor 3
System memory 512MB 1GB
GPU
SVGA
(800 x 600)
DX9
Capable
Aero-capable
Graphics memory 32MB 128MB
HDD 20GB 40GB
HDD free space 15GB
Optical drive CD-ROM 4 DVD-ROM 4
Networking Internet access-capable
Audio Audio output capability
1, 2

Density Matters
“Give Give Vista as much memory as you can, and it will thank
you by serving you quicker.” quicker.
Tom’s Tom s Hardware, Windows Vista's SuperFetch and ReadyBoost
Analyzed, January 31, 2007
http://www.tomshardware.com/2007/01/31/windows-vista
http://www.tomshardware.com/2007/01/31/windows vista-
superfetch-and
superfetch and-readyboostanalyzed/index.html
readyboostanalyzed/index.html

Windows Vista RTM Test Results
Memory utilization is
minimized with more
system memory
installed
SuperFetch exhausts
DRAM memory
before using NAND
memory
2GB appears to be
optimal DRAM
density for Vista
Multiple programs running
Percentage
100.00%
90.00%
80.00%
70.00%
60.00%
50.00%
40.00%
30.00%
20.00%
10.00%
0.00%
88.00%
Memory Utilization Percentage
65.00% 63.00%
57.00%
512MB 1GB 1.5GB 2GB
Memory Specification
Lower number means your system has more resources
available for additional tasks
Two Web browsers, Windows Media Player, Adobe Photoshop with 445MB 445MB
file
open, and Trend Virus Protection
System
Specifications
Inspiron 6000
Intel 915GM/PM
Vista RC2
Intel Pentium M 1.7 Ghz
ATI Mobility Radeon X300
80GB Fujitsu ATA

Vista Ready Boost C&P Lab Results
With 2x CT3264AA667 512MB of DRAM installed:
Ready Boost disabled Ready Boost enabled
1:20.04 38.23 sec
1:09.48 33.23 sec
1:15.56 29.81 sec
1:06.06 44.46 sec
With 2x CT6464AA667 1024MB of DRAM installed:
Ready Boost disabled Ready Boost enabled
8.39 sec 7.43 sec
8.18 sec 7.29 sec
8.56 sec 6.50 sec
7.81 sec 7.51 sec

Vista Ready Boost C&P Lab Results
With 2x CT12864AA667 2048MB of DRAM installed:
Ready Boost disabled Ready Boost enabled
6.73 sec 5.57 sec
5.93 sec 5.14 sec
With 4x CT12864AA667 4096MB of DRAM installed:
Ready Boost disabled Ready Boost enabled
21.21 sec 7.07 sec
5.48 sec 6.29 sec
2GB DRAM achieves the peak performance gain for DRAM density
in Vista systems using Ready Boost

DRAM Density Increases CPU Efficiency
As memory density increases, memory utilization decreases
As memory density increases, processor utilization goes up
More memory drastically increases the efficiency of your processor processor
System Specifications Motherboard: Evga NF68 Chipset: nVidia 680i SLI Processor: Intel Pentium 4 2.8GHZ Video: ATI Radeon X1900XTX
PCIE 512MB Hard Drive:WD 80GB OS: Windows Vista Ultimate DRAM: Crucial DDR2 6400 Real World Test Processes running to generate
utilization: Nero Recode, ADOBE WITH 445 MEG FILE OPEN, 2 WEBSITES OPEN

Dual-Die Dual Die Stacking Technology
Typical monolithic FBGA packages utilize BOC
(board board-on on-chip chip) ) technology
Typical dual-die dual die FBGA packages utilize COB
(chip-on (chip on-board) board) technology
1.2mm
thick
Supports
DDR3 data
rates

Dual-Die Dual Die Package Construction
Maximum aximum Thickness = 1.35mm
RDL = Redistribution layer; center wire bond
pads are redistributed to perimeter of die
through a metal layer to facilitate stacking
Die
Die
Substrate
Top view of a typical RDL layer
Wire
Bonds

Dual-Die Dual Die Photo
Two die complete with wire bond prior to encapsulation

Power Consumption
4X density increase with little to no power increase
512Mb-based 1GB
and 2GB RDIMMs
Watts (per Slot)
18
16
14
12
10
8
6
4
High Speed RDIMMs
DDR2-800 DDR2-667
8GB (QR x4) - U48B
4GB (DR x4) - U48B
2GB (DR x4) - U37Y
1GB (SR x4) - U37Y
2GB (DR x8) - U48B
1GB (SR x8) - U48B
Power estimates reflect a maximum DRAM utilization of
67% with a BL = 4 and register/PLL power of 1.5W
Converting from 512Mb to 1Gbbased
reduces power by over 50%

Estimated WC power
Using (1Gb) Datasheet Values
Watts per Slot
25.00
20.00
15.00
10.00
5.00
0.00
QR x4
DR x4 (DDR3)
DR x4 (DDR2)
SR x4
DR x8
SR x8
DDR3 Power by R/C and Bandwidth
DDR3-800 DDR3-1067 DDR3-1333
DDR2-400 DDR2-533 DDR2-667 DDR2-800
DDR3-1333 is slightly higher than DDR2-800 and
about 2.2W more than DDR2-667
Reflects a sustained channel bandwidth of 65% maximum DRAM, 2x READs to
WRITEs distributed evenly through all ranks, closed page, single slot populated,
PLL/register package included
DDR3 (DR x4)
DDR2 (DR x4)
DDR3-1067 is about equal to DDR-667

Introduction to DDR3

DDR2 to DDR3 Comparison
Standard Features
Features/Options DDR2 DDR3 Comments
Pin-out/Package
Voltage
60-ball; x4, x8
84-ball; x16
FBGA only
1.8V
1.8V I/O
78-ball; x4, x8
96-ball; x16
FBGA only
1.5V
1.5V I/O
Densities 256Mb–4Gb 512Mb–8Gb
Internal banks
Prefetch
(MIN READ burst)
4 (256Mb, 512Mb)
8 (1Gb, 2Gb, 4Gb)
4-bit
(2 clocks)
8 (512Mb, 1Gb, 2Gb,
4Gb, 8Gb)
8-bit
(4 clocks)
Independent pin-out for x4/x8
and x16 (simplifies module
design)
Reduces memory system
power demand
High‐density components
enable large capacity memory
subsystems
Larger density per monolithic
package, 8 banks is standard
Reduced core speed
dependency for better yield
t CK – DLL enabled 125 MHz to 400 MHz 300 MHz to 800 MHz Supports higher data rates

DDR2 to DDR3 Comparison
Standard Features
Features/Options DDR2 DDR3 Comments
Burst length (BL) BL4, BL8 BC4, BL8
Burst type Fixed, via LMR
Speed (data pin)
Additive Latency
(AL)
(Posted CAS)
READ Latency
400, 533,
667, 800 Mb/s
AL options
(0, 1, 2, 3, 4)
AL + CL
CL = 3, 4, 5, 6
WRITE Latency RL - 1
(1) Fixed, via MRS
(2) OTF, “on-the-fly”
800, 1066,
1333, 1600 Mb/s
AL options
0, CL - 1, CL - 2
AL + CL
CL = 5, 6, 7, 8, 9, 10
AL + CWL
CWL = 5, 6, 7, 8
BC4 provides relief from some “BL8”
requirements
OTF allows switching between BC4
and BL8 without MRS command
Migration to higher‐speed I/O
Mainly used in server applications to
improve command bus efficiency
800(-25E) 5-5-5 1333(-15F) 8-8-8
800(-25) 6-6-6 1333(-15E) 9-9-9
1066(-187E) 7-7-7 1600(-125E) 9-9-9
1066(-187) 8-8-8 1600(-125) 10-10-10
Reduces latency combinations, one
latency per t CK range

DDR2 to DDR3 Comparison
Standard Features
Features/Options DDR2 DDR3 Comments
Data strobes
Data bus termination
Rtt
Single-ended or
differential
on­die termination
(ODT)
opt. on MB
Rtt values 50, 75, 150 ohm
Rtt allowed
Read, writes,
standby
Differential only Reduce data strobe crosstalk
on­die termination
(ODT)
opt. on MB
120, 60, 40, 30,
20 ohm
Optimized for higher data rates
Support higher data rates
Writes, standby DDR3 does not allow during reads
Dynamic ODT None 120, 60 ohm Supports 2-slot; writes only
DQ driver impedance 18 ohm 34 ohm
Driver/ODT
calibration
None External resistor
Optimized for 2-slot and pt-to-pt
systems
Improves accuracy over voltage
and temperature

DDR2 to DDR3 Comparison
Standard Features
Features/Options DDR2 DDR3 Comments
Multi-purpose register
(MPR)
None
Write leveling None
Four registers – 2
defined, 2 RFU
DQS captures CK, DQ
drives out CK’s state
RESET# None Dedicated input
Modules
240-pin UDIMM,
RDIMM, FBDIMM;
200-pin SODIMM
240-pin UDIMM; RDIMM
and FBDIMM TBD;
204-pin SODIMM
Provides specialty
readouts
De-skews fly-by layout
used by modules
Disable outputs,
resets DRAM
Similar dimensions as
DDR2

DDR2 to DDR3 Comparison
Optional Features
Features/Options DDR2 DDR3 Comments
Automatic self refresh
(ASR)
t CK – DLL disabled
ODTS, via MPR
(On-die temp sensor)
None Optional
Undefined
(optional)
None
128 kHz to 125 MHz
(optional)
2 readout points
(3 states – 1X, 2X, >2X
refresh rate), optional
Automatically adjust
refresh rate during self
refresh mode
Provides some guidance
for DLL disabled mode, if
supported
ODTS to trip at refresh
points, with 2C grace
margin. 85C, 95C

DDR3 Performance Timeline
DDR3 data rate and latency timeline
Speed Latency t AA (ns) Speed Latency t AA (ns) Speed Latency t AA (ns)
1067
800
2007
2008
CL7 13.125 CL8 12 1600 CL10 12.5
1333
CL8 15 CL9 13.5 CL8 12
1333
CL5 12.5 1067 CL7 13.125 CL9 13.5
CL6 15 800 CL5 12.5 1067 CL7 13.125
Fastest speed grade driven by high-end high end desktop
Mainstream will not pay for speed
Notebook and server segments tend to follow
mainstream desktop
2009
15ns latencies not expected to be required for 1333 and
above

© 2007 Microsoft Corporation. All rights reserved. Microsoft, Windows, Windows Vista and other product names are or may be registered trademarks and/or trademarks in the
U.S. and/or other countries. The information herein is for informational purposes only and represents the current view of Microsoft Corporation as of the date of this
presentation. Because Microsoft must respond to changing market conditions, it should not be interpreted to be a commitment on the part of Microsoft, and Microsoft cannot
guarantee the accuracy of any information provided after the date of this presentation. MICROSOFT MAKES NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, AS
TO THE INFORMATION IN THIS PRESENTATION.