Intel Itanium Processor 9300 Series and 9500 Series

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Introduction Figure 1-1. Intel ® Itanium ® Processor 9300 Series Processor Block Diagram Core0 Core1 Core2 Core3 CPE0 CPE1 CPE2 CPE3 Intel® SMI Intel® SMI Pbox PZ0 Zbox0 Bbox0 8 7 3 2 Rbox 0xA 0 1 6 9 5 4 0xB Bbox1 Zbox1 Pbox PZ1 Intel® SMI Intel® SMI Pbox PH4 Pbox PR 0 Pbox PR1 Pbox PR 2 Pbox PR 3 Pbox PH5 Intel® QPI Intel® QPI Intel® QPI Intel® QPI Intel® QPI Intel® QPI 1.2.2 Intel ® Itanium ® Processor 9500 Series Overview The Intel ® Itanium ® Processor 9500 Series is an eight core architecture. It supports up to eight cores, each with its own First Level Cache (FLC) and Mid Level Cache (MLC), both of which are split into instruction and data caches (FLI/FLD and MLI/MLD, respectively). The Last Level Cache (LLC) is shared among the cores and supports up to 32 MB. Also supported are the following page sizes for purges or inserts: 4K, 8K, 16K, 64K, 256K, 1M, 4M, 16M, 64M, 256M, 1G, 4G. The architecture interfacing the cores to the system is referred to as the uncore. Each Intel ® Itanium ® Processor 9500 Series core interfaces to the Ring. The Ring provides connectivity to the Last Level Cache via the Cache Controllers (Cboxes). The Ring also provides connectivity to Intel QPI via Ring/Sbox. The Sbox and Cbox provide the supports for the two Intel QPI Caching Agents. The processor has two Home Agents (Bbox). The Bbox interfaces between the memory controller and the Intel ® QuickPath Interconnect and supports a directory cache. Each memory controller supports two Intel ® Scalable Memory Interconnects (Intel ® SMI) in lockstep. The Intel SMI are the interconnects to Scalable Memory Buffer. The Intel ® Itanium ® Processor 9500 Series processor supports six Intel ® QuickPath Interconnects at the socket, four full width and two half width. The Caching Agent, Home Agent, and Intel ® QuickPath Interconnects are connected via a 10-port Crossbar Router, each port supporting the Intel ® QuickPath Interconnect protocol. Figure 1-2 shows the processor block diagram. 16 Intel ® Itanium ® Processor 9300 Series and 9500 Series Datasheet
Introduction Figure 1-2. Intel ® Itanium ® Processor 9500 Series Processor Block Diagram The Intel QPI viral and poison fields are used to flag corrupted system state and bad data accordingly. Once it has “gone viral”, an Intel QPI agent will set the viral field within all packet headers. Viral mode is entered in three ways: receiving a viral packet, upon a detecting fatal/panic error, or when a global viral signal (from Cboxes) is asserted. Viral is cleared on Reset. Poisoning is used to indicate bad data on a per-flit basis. Poison does not indicate corrupted system coherency, but rather that a particular block of data is not reliable. Intel ® Itanium ® Processor 9500 Series PAL's Demand Based Switching (DBS) support includes implementations of Power/Performance states (P-states) and Halt states (Cstates). For the PAL Halt state interface and architected specifications of the PAL P- state interface, see the Intel ® Itanium ® Architecture Software Developer's Manual, Volume 2, Section 11.6. PAL controls the Intel ® Itanium ® Processor 9500 Series processor power through a special built-in microcontroller that manipulates voltage and frequency. PAL communicates requested P-states to this controller through internal registers. As shown in Figure 1-3, Itanium architecture-based firmware consists of several major components: Processor Abstraction Layer (PAL), System Abstraction Layer (SAL), Unified Extensible Firmware Interface (UEFI) and Advanced Configuration and Power Interface (ACPI). PAL, SAL, UEFI and ACPI together provide processor and system initialization for an operating system boot. PAL and SAL provide machine check abort handling. PAL, SAL, UEFI and ACPI provide various run-time services for system functions which may vary across implementations. The interactions of the various services that PAL, SAL, UEFI and ACPI provide are illustrated in Figure 1-3. In the context of this model and throughout the rest of this chapter, the System Abstraction Layer (SAL) is a firmware layer which isolates operating system and other higher level software from implementation differences in the platform, while PAL is the firmware layer that abstracts the processor implementation. Intel ® Itanium ® Processor 9300 Series and 9500 Series Datasheet 17
Page 1 and 2: Intel ® Itanium ® Processor 9300
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Intel Itanium Processor 9300 Series and 9500 Series

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