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Intel Itanium Processor 9300 Series and 9500 Series

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Electrical Specifications<br />

7. The FMB remote sense tolerance is ±2.5% for DC to 20 MHz at the package, where ±1.5% is allotted for a DC to 1 MHz range<br />

<strong>and</strong> an additional ±1.0% for 1 MHz to 20 MHz. Similarly, ±6.4% is allotted for DC to 20 MHz at the die. It is expected that VCCIO<br />

regulators meet ±1.5% at the remote sense location based on the general remote sense termination point location as described<br />

in Figure 2-16 VR Sense Point (Representation). For future processor compatibility, it is strongly recommended that the platform<br />

query the PIROM to assure VCCIO is set to the appropriate level prior to powering up the VCCIO supply.<br />

8. All voltage regulation measurements taken at remote sense termination points.<br />

9. For peak-to-peak Ripple <strong>and</strong> Noise (R&N) measured with full b<strong>and</strong>width (BW) of the scope (Min 1 GHz BW scope is required):<br />

set scope diff probe <strong>and</strong> the scope at full BW (capture waveform A, channel 1).<br />

10.For peak-to-peak Ripple <strong>and</strong> Noise (R&N) measured above 1 MHz:<br />

Step 1 = set both: scope diff probe <strong>and</strong>/or the scope at 1 MHz BW limit (capture waveform B, channel 2)<br />

Step 2 = calculate A-B (use scope Math function: subtract channel 1 - channel 2).<br />

Table 2-19.<br />

FMB 170W <strong>and</strong> 130W Current Specifications for the <strong>Intel</strong> ® <strong>Itanium</strong> ® <strong>Processor</strong><br />

<strong>9500</strong> <strong>Series</strong><br />

Symbol Parameter Max Min Units Notes<br />

I CC_CORE I CC for core 35.0 A 1<br />

I CC_CORE_TDC Thermal Design Current for Core 30.0 A 1, 2<br />

I CC_CORE_STEP Max Load step for core 14.62 A 1, 3<br />

d ICC_CORE/dt Slew rate for core at Ararat output 34.4 A/us 1<br />

I CC_UNCORE I CC for uncore 80.0 A<br />

I CC_UNCORE_TDC Thermal Design Current for Uncore 75.0 A 4<br />

I CC_UNCORE_STEP Max Load step for uncore 30.4 A 5<br />

dI CC_UNCORE/dt Slew rate for uncore at Ararat output 168.0 A/us<br />

I CC_IO I CC for processor I/O 17.2 A 6<br />

d ICC_IO/dt Slew rate for IO at the package pin 54.0 A/us<br />

I CC_IO_STEP Max Load step for max slew rate 5.1 A 7<br />

T CC_IO_STEP Time between steps 4.7 us 7<br />

I CC_Analog I CC for processor Analog 4 A<br />

I CC33_SM I CC33 for main supply 200 mA<br />

Notes:<br />

1. Values per core pair.<br />

2. ICC_CORE_TDC is the sustained (DC equivalent) current that the processor core is capable of drawing indefinitely <strong>and</strong> should be<br />

used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for monitoring its<br />

temperature <strong>and</strong> asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform the processor<br />

<strong>and</strong> platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor. Please see<br />

the Ararat II Voltage Regulator Module Design Guide for further details. The processor is capable of drawing ICC_CORE_TDC<br />

indefinitely.<br />

3. During system power on, the pulse inrush (ICC_CORE_STEP) can be as high as 35A peak-to-peak.<br />

4. ICC_UNCORE_TDC is the sustained (DC equivalent) current that the processor uncore is capable of drawing indefinitely <strong>and</strong><br />

should be used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for<br />

monitoring its temperature <strong>and</strong> asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform<br />

the processor <strong>and</strong> platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor.<br />

Please see the Ararat II Voltage Regulator Module Design Guide for further details. The processor is capable of drawing<br />

ICC_UNCORE_TDC indefinitely. This parameter is based on design characterization <strong>and</strong> is not tested.<br />

5. During system power on, the pulse inrush (ICC_UNCORE_STEP) can be as high as 40A peak-to-peak.<br />

6. The ICC_IO current specification applies to the total current from VCCIO pins.<br />

7. The max load step represents the maximum current required during <strong>Intel</strong> ® QPI <strong>and</strong> <strong>Intel</strong> ® SMI port initialization. The min time<br />

between steps represents the time between <strong>Intel</strong> ® QPI <strong>and</strong> <strong>Intel</strong> ® SMI initialization.<br />

2.6.3 <strong>Intel</strong> ® <strong>Itanium</strong> ® <strong>Processor</strong> <strong>9300</strong> <strong>Series</strong> Uncore, Core, <strong>and</strong><br />

Cache Tolerances<br />

2.6.3.1 Uncore Static <strong>and</strong> Transient Tolerances<br />

Table 2-20 <strong>and</strong> Figure 2-10 specify static <strong>and</strong> transient tolerances for the uncore<br />

outputs.<br />

44 <strong>Intel</strong> ® <strong>Itanium</strong> ® <strong>Processor</strong> <strong>9300</strong> <strong>Series</strong> <strong>and</strong> <strong>9500</strong> <strong>Series</strong> Datasheet

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