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Intel Itanium Processor 9300 Series and 9500 Series

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Introduction<br />

Description<br />

<strong>Intel</strong> ® <strong>Itanium</strong> ® <strong>Processor</strong> <strong>9300</strong><br />

<strong>Series</strong><br />

<strong>Intel</strong> ® <strong>Itanium</strong> ® <strong>Processor</strong> <strong>9500</strong><br />

<strong>Series</strong><br />

Memory patrolling Supported Supported<br />

Memory migration Supported Supported<br />

Support for mixing of x4 <strong>and</strong> x8 on the<br />

same DDR channel<br />

Not Supported<br />

Supported<br />

Online/Offline CPU (OS assisted) Supported Supported<br />

Online/Offline Memory (OS assisted) Supported Supported<br />

Online/Offline I/O Hub Supported Supported<br />

Thermal Design Power (TDP) SKUs 130W, 155W, 185W 130W <strong>and</strong> 170W<br />

Notes:<br />

1. OEM responsible for specifying platform-specific retraining interval.<br />

2. Electrical isolation only, no physical add/remove supported.<br />

3. Assume spare is installed.<br />

1.4 <strong>Processor</strong> Abstraction Layer<br />

The <strong>Intel</strong> ® <strong>Itanium</strong> ® <strong>Processor</strong> <strong>9300</strong> <strong>Series</strong> <strong>and</strong> <strong>Intel</strong> ® <strong>Itanium</strong> ® <strong>Processor</strong> <strong>9500</strong> <strong>Series</strong><br />

require implementation-specific <strong>Processor</strong> Abstraction Layer (PAL) firmware. PAL<br />

firmware supports processor initialization, error recovery, <strong>and</strong> other functionality. It<br />

provides a consistent interface to system firmware <strong>and</strong> operating systems across<br />

processor hardware implementations. The <strong>Intel</strong> ® <strong>Itanium</strong> ® Architecture Software<br />

Developer’s Manual, Volume 2: System Architecture, describes PAL. Platforms must<br />

provide access to the firmware address space <strong>and</strong> PAL at reset to allow the processors<br />

to initialize.<br />

The System Abstraction Layer (SAL) firmware contains platform-specific firmware to<br />

initialize the platform, boot to an operating system, <strong>and</strong> provide runtime functionality.<br />

Further information about SAL is available in the <strong>Intel</strong> ® <strong>Itanium</strong> ® <strong>Processor</strong> Family<br />

System Abstraction Layer Specification.<br />

1.5 Mixing <strong>Processor</strong>s of Different Frequencies <strong>and</strong><br />

Cache Sizes<br />

All <strong>Intel</strong> ® <strong>Itanium</strong> ® <strong>Processor</strong> <strong>9300</strong> <strong>Series</strong> processors <strong>and</strong> <strong>Intel</strong> ® <strong>Itanium</strong> ® <strong>Processor</strong><br />

<strong>9500</strong> <strong>Series</strong> in the same system partition are required to have the same last level<br />

cache size <strong>and</strong> identical core frequency. Mixing processors of different core frequencies,<br />

cache sizes, <strong>and</strong> mixing <strong>Intel</strong> ® <strong>Itanium</strong> ® <strong>Processor</strong> <strong>9300</strong> <strong>Series</strong> with <strong>Intel</strong> ® <strong>Itanium</strong> ®<br />

<strong>Processor</strong> <strong>9500</strong> <strong>Series</strong> is not supported <strong>and</strong> has not been validated by <strong>Intel</strong>. Operating<br />

system support for multiprocessing with mixed components should also be considered.<br />

1.6 Terminology<br />

In this document, “the processor” refers to the <strong>Intel</strong> ® <strong>Itanium</strong> ® <strong>Processor</strong> <strong>9300</strong> <strong>Series</strong><br />

<strong>and</strong>/or <strong>Intel</strong> ® <strong>Itanium</strong> ® <strong>Processor</strong> <strong>9500</strong> <strong>Series</strong>, unless otherwise indicated.<br />

An ‘_N’ notation after a signal name refers to an active low signal. This means that a<br />

signal is in the active state (based on the name of the signal) when driven to a low<br />

level. For example, when RESET_N is low, a processor reset has been requested. When<br />

NMI is high, a non-maskable interrupt has occurred. In the case of lines where the<br />

name does not imply an active state but describes part of a binary sequence (such as<br />

20 <strong>Intel</strong> ® <strong>Itanium</strong> ® <strong>Processor</strong> <strong>9300</strong> <strong>Series</strong> <strong>and</strong> <strong>9500</strong> <strong>Series</strong> Datasheet

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