Intel Itanium Processor 9300 Series and 9500 Series

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Electrical Specifications Table 2-5. Intel ® Itanium ® Processor 9300 Series Transmitter Parameter Values for Intel ® QuickPath Interconnect and Intel SMI Channels @ 4.8 GT/s (Sheet 2 of 2) Symbol Parameter Min Nom Max Units Notes TX DUTY-CYCLE-PIN T TX-DATA-CLK-SKEW-PIN TX ACC-JIT-N_UI-1E-9 Transmitter clock or data duty cycle at the pin. Transmit duty cycle at the pin, defined as UI to UI jitter as specified by the Intel ® QPI Electrical Specification, Rev 1.0. Delay of any data lane relative to clock lane, as measured at Tx output Peak-to-peak accumulated jitter out of any TX data or clock over 0
Electrical Specifications Table 2-6. Intel ® Itanium ® Processor 9300 Series Receiver Parameter Values for Intel ® QuickPath Interconnect and Intel ® SMI Channels @ 4.8 GT (Sheet 2 of 2) Symbol Parameter Min Nom Max Units Notes T RX-eye-pin Minimum eye width at pin for clk and data 0.6 UI 4 QPI BER Lane Bit Error Rate per lane valid for 4.8 and 6.4 GT/s 1.0E-14 Events SMI BER Lane Bit Error Rate per lane valid for 4.8 and 6.4 GT/s 1.0E-12 Events Notes: 1. Parameter value at 1/4 Intel ® QPI Refclk. 2. Parameter value at full Intel ® QPI Refclk. 3. The termination small signal resistance; tolerance over the entire signalling voltage range shall not exceed ±5 ohms with regard to the average of the values measured in the high output voltage state and the low output voltage state for that pin. 4. HVM guaranteed error free value for stressed PRBS signaling across PVT. Link BER is the dominant spec of which eye dimensions are only one factor, and improving another factor could compensate for eye height or width. 5. HVM guaranteed error free value for stressed ‘1010 signaling across PVT. Link BER is the dominant spec of which eye dimensions are only one factor, and improving another factor could compensate for eye height or width. 6. See Figure 2-8. Figure 2-6. TX Equalization Diagram C -1 C 2 Vpost A C -1 C 0 C 1 C 2 C 0 C 1 Vsust 0 Vpre -A Vpre = A(C -1 - C 0 -C 1 -C 2) Vpost = A(C -1 + C 0 -C 1 -C 2) Vsust = A(C -1 + C 0 + C 1 + C 2 ) C 0 = 1 – sum of abs value of other coeficents Vpost - Vpre – Vsust = |C -1| + |C 0 |+ |C 1 |+ |C 2| = 1 %Peaking = Vpost/Vsust Example: A=500mV, C -1= -0.035, C 0= 0.685, C 1= -0.28, C 2= 0 Vpre = 0.500(-0.035 – 0.685 + 0.28) = 0.5(-0.44) = -220mV Vpost = 0.500(-0.035 + 0.685 + 0.28) = 0.5(0.93) = 465mV Vsust= 0.500(-0.035 + 0.685 – 0.28) = 0.5(0.37) = 185mV TXEQ-BOOST = 20log(Vpost/Vsust) = 20log(465/185) = 8dB Peaking = 465/185 = 251% Intel ® Itanium ® Processor 9300 Series and 9500 Series Datasheet 31
Page 1 and 2: Intel ® Itanium ® Processor 9300
Page 3 and 4: Contents 1 Introduction............
Page 5 and 6: Figures 1-1 Intel ® Itanium ® Pro
Page 7 and 8: 2-33 SMBus and Serial Presence Dete
Page 9 and 10: Introduction 1 Introduction 1.1 Ove
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Page 15 and 16: Introduction replay can be initiate
Page 17 and 18: Introduction Figure 1-2. Intel ® I
Page 19 and 20: Introduction 1.3 Processor Feature
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Mechanical Specifications 4.2 Intel
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Thermal Specifications 5 Thermal Sp
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Thermal Specifications Table 5-1. T
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Thermal Specifications QR_CSR_IPF_T
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Thermal Specifications 5.2 Package
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System Management Bus Interface 6 S
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System Management Bus Interface Fig
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Signal Definitions 7 Signal Definit
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1 Introduction.....................
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Intel Itanium Processor 9300 Series and 9500 Series

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