Intel Itanium Processor 9300 Series and 9500 Series

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Electrical Specifications Figure 2-7. TX Return Loss Figure 2-8. RX Return Loss 2.4.2 Intel ® Itanium ® Processor 9500 Series Requirements for Intel ® QuickPath Interconnect for 4.8 and 6.4 GT/s The applicability of this section applies to Intel ® Itanium ® Processor 9500 Series. This section contains information for slow boot up speed (1/4 frequency of the reference clock), 4.8 GT/s, and 6.4 GT/s, for Intel ® QPI and Intel ® SMI. For Intel ® QPI slow boot up speed, the signaling rate is defined as 1/4 the rate of the system reference clock. For example, a 133 MHz system reference clock would have a forwarded clock frequency of 33.33 MHz and the signaling rate would be 66.67 MT/s. 32 Intel ® Itanium ® Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications The transfer rates available for the processor are shown in Table 2-7. Transmitter and receiver parameters for Intel ® QPI slow mode, Intel ® QPI and Intel ® SMI are shown in Table 2-8 and Table 2-9 respectively. Table 2-7. Intel ® Itanium ® Processor 9500 Series Clock Frequency Table Intel ® QuickPath Interconnect Forwarded Clock Frequency Intel ® QuickPath Interconnect Data Transfer Rate 33.33 MHz 66.66 MT/s (see note 1) 2.40 GHz 4.8 GT/s 3.2 GHz 6.4 GT/s Notes: 1. This speed is the 1/4 SysClk Frequency. The applicability of this section applies to Intel ® QPI for the Intel ® Itanium ® Processor 9500 Series. This section contains information for slow boot up speed (1/4 frequency of the reference clock), 4.8 GT/s, and 6.4 GT/s. Specifications for link speed independent specifications are called out in Table 2-8. Electrical specifications for Transmit and Receive for 4.8 GT/s are captured in Table 2-9 and for 6.4 GT/s are captured in Table 2-10. Table 2-8. Intel ® Itanium ® Processor 9500 Series Link Speed Independent Specifications (Sheet 1 of 2) Symbol Parameter Min Nom Max Unit Notes UIavg Average UI size at “G” GT/s (Where G = 4.8, 6.4, and so on) 0.999 * nominal 1000/G 1.001 * nominal psec T slew-rise-fall-pin ΔZ TX_LOW_CM_DC ΔZ RX_LOW_CM_DC N MIN-UI-Validation Defined as the slope of the rising or falling waveform as measured between ±100mV of the differential transmitter output, for any data or clock Defined as: (max(Z TX_LOW_CM_DC ) - min(Z TX_LOW_CM_DC )) / Z TX_LOW_CM_DC expressed in %, over full range of Tx single ended voltage Defined as: (max(Z TX_LOW_CM_DC ) - min(Z TX_LOW_CM_DC )) / Z TX_LOW_CM_DC expressed in %, over full range of Tx single ended voltage # of UI over which the eye mask voltage and timing spec needs to be validated 9 20 V/nsec -6 6 % of Z TX_LOW_CM_DC -6 0 6 % of Z TX_LOW_CM_DC 1,000,000 Z TX_HIGH_CM_DC Single ended DC impedance to GND for either D+ or D- of any data bit at Tx 4k Ω Z RX_HIGH_CM_DC Single ended DC impedance to GND for either D+ or D- of any data bit at Rx 4k Ω 1 Intel ® Itanium ® Processor 9300 Series and 9500 Series Datasheet 33
Page 1 and 2: Intel ® Itanium ® Processor 9300
Page 3 and 4: Contents 1 Introduction............
Page 5 and 6: Figures 1-1 Intel ® Itanium ® Pro
Page 7 and 8: 2-33 SMBus and Serial Presence Dete
Page 9 and 10: Introduction 1 Introduction 1.1 Ove
Page 11 and 12: Introduction Intel ® Itanium ® Pr
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Page 19 and 20: Introduction 1.3 Processor Feature
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Page 23 and 24: Electrical Specifications 2 Electri
Page 25 and 26: Electrical Specifications Table 2-2
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Mechanical Specifications 4 Mechani
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Mechanical Specifications 4.2 Intel
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Mechanical Specifications 4.3 Proce
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Thermal Specifications 5 Thermal Sp
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Thermal Specifications Table 5-1. T
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Thermal Specifications QR_CSR_IPF_T
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Thermal Specifications 5.2 Package
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System Management Bus Interface 6 S
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System Management Bus Interface Fig
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System Management Bus Interface 6.4
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Signal Definitions 7 Signal Definit
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Signal Definitions Table 7-1. Signa
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1 Introduction.....................
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1-1 Intel ® Itanium ® Processor 9
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Intel Itanium Processor 9300 Series and 9500 Series

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