Intel Itanium Processor 9300 Series and 9500 Series

Electrical Specifications
Table 2-1.
Signals with R TT
Signal
Termination
CSI[3:0]R[P/N]Dat[19:0]
CSI[5:4]R[P/N]Dat[9:0]
CSI[3:0]T[P/N]Dat[19:0]
CSI[5:4]T[P/N]Dat[9:0]
CSI[5:0]R[P/N]Clk
CSI[5:0]T[P/N]Clk
FBD0NBICLK[A/B][P/N]0
FBD1NBICLK[C/D][P/N]0
FBD0SBOCLK[A/B][P/N]0
FBD1SBOCLK[C/D][P/N]0
FBD0NBI[A/B][P/N][13:0]
FBD1NBI[C/D][P/N][13:0]
FBD0SBO[A/B][P/N][10:0]
FBD1SBO[C/D][P/N][10:0]
XDPOCPD_N[7:0]
TRIGGER_N[1:0]
XDPOCPFRAME_N
XDPOCP_STRB_IN_N
PRBMODE_REQST_N
XDPOCP_STRB_OUT_N
PRBMODE_RDY_N
VSS
VSS
VCCIO
2.2 Signal Groups
The signals are grouped by buffer type and similar characteristics as listed in Table 2-2.
The buffer type indicates which signaling technology and specifications apply to the
signals.
Table 2-2. Signal Groups (Sheet 1 of 3)
Signal Group Buffer Type Signals 1, 2, 3
Differential System Reference Clock
Differential CMOS In Differential Pair SYSCLK, SYSCLK_N;
SYSUTST_REFCLK_N, SYSUTST_REFCLK
Intel ® QuickPath Interconnect Signal Groups
Differential Input CSI[3:0]R[P/N]Dat[19:0], CSI[5:4]R[P/N][9:0]
CSI[5:0]R[P/N]CLK
Differential Output CSI[3:0]T[P/N]Dat[19:0], CSI[5:4]T[P/N][9:0],
CSI[5:0]T[P/N]CLK
FB-DIMM Signals
Differential Input FBD0NBICLK[A/B][P/N]0
FBD1NBICLK[C/D][P/N]0
Differential Output FBD0SBOCLK[A/B][P/N]0
FBD1SBOCLK[C/D][P/N]0
Differential Input FBD0NBI[A/B][P/N][13:0]
FBD1NBI[C/D][P/N][13:0]
Differential Output FBD0SBO[A/B][P/N][10:0]
FBD1SBO[C/D][P/N][10:0]
TAP
24 Intel ® Itanium ® Processor 9300 Series and 9500 Series Datasheet