Intel Itanium Processor 9300 Series and 9500 Series

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Electrical Specifications Table 2-8. Intel ® Itanium ® Processor 9500 Series Link Speed Independent Specifications (Sheet 2 of 2) Symbol Parameter Min Nom Max Unit Notes Z TX_LINK_DETECT Link Detection Resistor 500 2000 Ω V TX_LINK_DETECT Link Detection Resistor Pull-up Voltage max VCCIO V T DATA_TERM_SKEW Skew between first to last 128 UI Z RX_LOW_CM_DC data termination meeting T INBAND_RESET_ SENSE Time taken by inband reset detector to sense Inband Reset 1.5 μs Tclk _DET Time taken by clock detector to observe clock stability 20K UI T CLK_FREQ_DET T Refclk-Tx-Variability T Refclk-Rx-Variability Time taken by clock frequency detector to decide slow vs. operational clock after stable clock Phase variability between reference Clk (at Tx input) and Tx output. Phase variability between reference Clk (at Rx input) and Rx output. 32 Reference Clock Cycles 500 psec 1000 psec L D+/D-RX-Skew Phase skew between D+ and D- lines for any data bit at Rx 0.03 UI BER Lane Bit Error Rate per lane valid for 4.8 and 6.4 GT/s 1.0E-14 Events Notes: 1. Used during initialization. It is the state of “OFF” condition for the receiver when only the minimum termination is connected. Table 2-9. Intel ® Itanium ® Processor 9500 Series Transmitter and Receiver Parameter Values for Intel ® QPI Channel at 4.8 GT/s (Sheet 1 of 2) Symbol Parameter Min Nom Max Unit Notes V Tx-diff-pp-pin Transmitter differential swing 900 1400 mV 1 Z TX_LOW_CM_DC DC resistance of Tx terminations at half the single ended swing (which is usually 0.25*V Tx-diff-pppin 37.4 50 Ω Z RX_LOW_CM_DC V Tx-cm-dc-pin V Tx-cm-ac-pin DC resistance of Rx terminations at half the single ended swing (which is usually 0.25*V Tx-diff-pppin 37.4 50 Ω Transmitter output DC common 0.23 0.27 Fraction of and V D- mode, defined as average of V D+ V Tx-diff-pp-pin Transmitter output AC common mode, defined as ((V D+ + V D- )/2 - V Tx-cm-dc-pin ) -0.0375 0.0375 Fraction of V Tx-diff-pp-pin 2 TX duty-pin Average of UI-UI jitter -0.055 0.055 UI TX jitUI-UI-1E-7-pin UI-UI jitter measured at Tx output -0.075 0.075 UI pins with 1E-7 probability TX jitUI-UI-1E-9-pin UI-UI jitter measured at Tx output pins with 1E-9 probability. -0.085 0.085 UI 34 Intel ® Itanium ® Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications Table 2-9. Intel ® Itanium ® Processor 9500 Series Transmitter and Receiver Parameter Values for Intel ® QPI Channel at 4.8 GT/s (Sheet 2 of 2) Symbol Parameter Min Nom Max Unit Notes TX clk-acc-jit-N_UI-1E-7 TX clk-acc-jit-N_UI-1E-9 T Tx-data-clk-skew-pin V Rx-diff-pp-pin T Rx-diff-pp-pin T Rx-data-clk-skew-pin V Rx-CLK V Rx-cm-dc-pin V Rx-cm-ac-pin p-p accumulated jitter out of transmitter over 0
Page 1 and 2: Intel ® Itanium ® Processor 9300
Page 3 and 4: Contents 1 Introduction............
Page 5 and 6: Figures 1-1 Intel ® Itanium ® Pro
Page 7 and 8: 2-33 SMBus and Serial Presence Dete
Page 9 and 10: Introduction 1 Introduction 1.1 Ove
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Page 17 and 18: Introduction Figure 1-2. Intel ® I
Page 19 and 20: Introduction 1.3 Processor Feature
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Page 23 and 24: Electrical Specifications 2 Electri
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Pin Listing Table 3-1. Pin List by
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Mechanical Specifications 4.2 Intel
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Mechanical Specifications 4.3 Proce
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Thermal Specifications 5 Thermal Sp
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Thermal Specifications Table 5-1. T
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Thermal Specifications QR_CSR_IPF_T
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Thermal Specifications 5.2 Package
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Thermal Specifications Table 5-5. S
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System Management Bus Interface 6 S
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System Management Bus Interface Tab
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System Management Bus Interface Fig
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System Management Bus Interface 6.4
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Signal Definitions 7 Signal Definit
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Signal Definitions Table 7-1. Signa
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1 Introduction.....................
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1-1 Intel ® Itanium ® Processor 9
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1-1 Intel ® Itanium ® Processor 9
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Intel Itanium Processor 9300 Series and 9500 Series

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