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Versa 5000 Series Service and Reference Manual - Support

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Technical Information 1-17<br />

VGA Controller<br />

The NeoMagic NM2160 is a PCI 128-bit Graphics Accelerator. The integrated programmable<br />

linear address feature accelerates the graphics user interface (GUI) performance.<br />

The controller also supports Hardware Multimedia <strong>and</strong> VESA interface st<strong>and</strong>ards. The<br />

controller provides advanced power management that helps to minimize power usage in<br />

the following modes:<br />

„ normal operation<br />

„ St<strong>and</strong>by (sleep) mode<br />

„ panel off power saving modes.<br />

Parallel Interface<br />

The PC87338VJG chip is a 100-pin Thin Quad Flat Plastic (TQFP) chip. The controller<br />

changes 8-bit parallel data into serial data <strong>and</strong> writes the data to the diskette. Conversely,<br />

the serial data is transmitted from the diskette into parallel data, where it remains until the<br />

read operation takes place.<br />

„ Additional PC87338VJG chip operations include:<br />

„ ISA compatibility<br />

„ low-power CMOS with enhanced power-down mode<br />

Keyboard Controller<br />

The keyboard controller (H8/3434) supports a PS/2-style keyboard <strong>and</strong>, mouse. Refer to<br />

Appendix A for keyboard interface connector pin assignments.<br />

When data is written to the output buffer, the controller generates an interrupt, <strong>and</strong> requests<br />

the CPU to receive the data. The controller automatically adds an even parity bit to the data<br />

sent <strong>and</strong> waits for a response. The device must acknowledge that the data was successfully<br />

received by sending a response to the controller for each byte of data received.<br />

PC CardBus Controller<br />

The Texas Instruments PCI1131 controller interfaces with the PCI bus, PC CardBus socket<br />

<strong>and</strong> configuration registers to provide:<br />

„ compliant with PCI 2.1 <strong>and</strong> 1995 PC card st<strong>and</strong>ards<br />

„ CardBus slots with hot insertion <strong>and</strong> removal<br />

„ independent Read <strong>and</strong> Write buffers for each direction<br />

„ burst transfers to maximize data throughput on the PCI CardBus bus.

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