F35-XXL Hardware description - Falcom
F35-XXL Hardware description - Falcom
F35-XXL Hardware description - Falcom
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<strong>F35</strong>-<strong>XXL</strong> HARDWARE DESCRIPTION VERSION 1.10<br />
6.2 Technical Description<br />
6.2.1 Receiver Architecture<br />
The GPS- Core in the FALCOM <strong>F35</strong>-<strong>XXL</strong>-SI is features of the SiRFstarII<br />
chipset. This complete 12 channel, WAAS-enabled GPS receiver provides a<br />
vastly superior position accuracy performance in a much smaller package.<br />
The SiRFstarII architecture builds on the high-performance SiRFstarI core,<br />
adding an acquisition accelerator, differential GPS processor, multipath<br />
mitigation hardware and satellite-tracking engine. The receiver delivers<br />
major advancements in GPS performance, accuracy, integration, computing<br />
power and flexibility.<br />
Figure 13: Receiver architecture of the integrated GPS-Core<br />
This confidential document is the property of FALCOM GmbH and may not be copied or circulated without permission.<br />
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