Curriculum Vitae - UCSD VLSI CAD Laboratory - UC San Diego

95. L. Carloni, A. B. Kahng, S. Muddu, A. Pinto, K. Samadi and P. Sharma, “Accurate Predictive
Interconnect Modeling for System-Level Design”, IEEE Transactions on Very Large Scale
Integration (VLSI) Systems 18(4) (2010), pp. 679-684.
96. K. Jeong, A. B. Kahng and K. Samadi, “Impact of Guardband Reduction on Design Outcomes: A
Quantitative Approach”, IEEE Transactions on Semiconductor Manufacturing 22(4) (2009), pp.
552-565.
97. A. B. Kahng, C.-H. Park, P. Sharma and Q. Wang, “Lens Aberration Aware Placement for
Timing Yield”, ACM Trans. on Design Automation of Electronic Systems 14(1) (2009), pp. 16:1
– 16:26.
98. A. B. Kahng, C.-H. Park, X. Xu and H. Yao, “Layout Decomposition Approaches for Double
Patterning Lithography”, IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems 29(6) (2010), pp. 939-952.
99. K. Jeong, A. B. Kahng, C.-H. Park and H. Yao, “Dose Map and Placement Co-Optimization for
Improved Timing Yield and Leakage Power”, IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems 29(7) (2010), pp. 1070-1082.
100. M. Gupta, K. Jeong and A. B. Kahng, “Timing Yield-Aware Color Reassignment and Detailed
Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography”, IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems 29(8) (2010), pp.
1229-1242.
101. P. Gupta, K. Jeong, A. B. Kahng and C.-H. Park, “Electrical Assessment of Lithographic Gate
Line-End Patterning”, SPIE J. Microlithography, Microfabrication and Microsystems 9(2) (2010),
pp. 023014-1–023014-19.
102. K. Jeong, A. B. Kahng, B. Lin and K. Samadi, “Accurate Machine Learning-Based On-Chip
Router Modeling”, IEEE Embedded Systems Letters 2(3) (2010), pp. 62-66.
103. A. B. Kahng, B. Li, L.-S. Peh and K. Samadi, “ORION 2.0: A Power-Area Simulator for
Interconnection Networks”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems
20(1) (2012), pp. 191-196.
104. K. Jeong, A. B. Kahng and C. J. Progler, “Cost-Driven Mask Strategies Considering Parametric
Yield, Defectivity and Production Volume”, SPIE J. Microlithography, Microfabrication and
Microsystems 10(3) (2011), pp. 033021-1–033021-12.
105. C.-K. Cheng, P. Du, X. Hu, A. B. Kahng, G. K. H. Pang, Y. Wang and N. Wong, “A Realistic
Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints”, IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems 31(1) (2012), pp.
109-120. (Correct author listing of this paper as given in Corrigendum, vol. 31(3) (2012), p. 452.)
106. A. B. Kahng, S. H. Kang, R. Kumar and J. Sartori, “Recovery-Driven Design: Exploiting Error
Resilience in Design of Energy-Efficient Processors”, IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems 31(3) (2012), pp. 404-417.
107. A. B. Kahng, S. Kang, R. Kumar and J. Sartori, “Enhancing the Efficiency of Energy-Constrained
DVFS Designs”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2012), to
appear.
108. A. B. Kahng, S. Kang, T. S. Rosing and R. Strong, “Many-Core Token-Based Adaptive Power
Gating”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32(8)
(2013), pp. 1288-1292.
109. T.-B. Chan, P. Gupta, A. B. Kahng and L. Lai, “Synthesis and Analysis of Design-Dependent
Ring Oscillator (DDRO) Performance Monitors”, IEEE Transactions on Very Large Scale
Integration (VLSI) Systems (2013), to appear.