Curriculum Vitae - UCSD VLSI CAD Laboratory - UC San Diego

Conference Papers
1. A. B. Kahng, “Fast Hypergraph Partition”, Proc. ACM/IEEE Design Automation Conf., June
1989, pp. 762-766.
2. A. B. Kahng, “Traveling Salesman Heuristics and Embedding Dimension in the Hopfield Model”,
Proc. IEEE/INNS Intl. Joint Conf. on Neural Networks, June 1989, pp. I-513 - I-520.
3. A. B. Kahng and G. Robins, “A New Class of Steiner Tree Heuristics with Good Performance:
the Iterated 1-Steiner Approach”, Proc. IEEE International Conf. on Computer-Aided Design,
November 1990, pp. 428-431 (Distinguished Paper Award; 18 awards out of 442 submissions).
4. A. B. Kahng, J. Cong and G. Robins, “High-Performance Clock Routing Based on Recursive
Geometric Matching”, Proc. ACM/IEEE Design Automation Conf., June 1991, pp. 322-327.
5. A. B. Kahng, “A Steiner Tree Construction for VLSI Routing”, Proc. IEEE/INNS Intl. Joint Conf.
on Neural Networks, July 1991, pp. I-133 - I-139.
6. A. B. Kahng and G. Robins, “Optimal Algorithms for Determining Regularity in Pointsets”, Proc.
Third Canadian Conf. on Computational Geometry, August 1991, pp. 167-170.
7. J. Cong, L. Hagen and A. B. Kahng, “Random Walks for Circuit Clustering”, Proc. 4th IEEE Intl.
ASIC Conf., September 1991, pp. 14.2.1 - 14.2.4.
8. J. Cong, A. B. Kahng and G. Robins, “On Clock Routing For General Cell Layouts”, Proc. 4th
IEEE Intl. ASIC Conf., September 1991, pp. 14.5.1 - 14.5.4.
9. J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong, “Performance-Driven Global
Routing for Cell Based IC's”, Proc. IEEE Intl. Conf. on Computer Design, October 1991, pp.
170-173.
10. A. B. Kahng, “An Effective Analog Approach to Steiner Routing”, Proc. IEEE Intl. Conf. on
Computer Design, October 1991, pp. 166-169.
11. L. Hagen and A. B. Kahng, “Fast Spectral Methods for Ratio Cut Partitioning and Clustering”,
Proc. IEEE Intl. Conf. on Computer-Aided Design, November 1991, pp. 10-13.
12. A. B. Kahng, “Exploiting Fractalness in Error Surfaces: New Methods for Neural Network
Learning”, Proc. IEEE Intl. Symp. on Circuits and Systems, May 1992, pp. 41-44.
13. A. B. Kahng, G. Robins and E. Walkup, “New Results and Algorithms for MCM Substrate
Testing”, Proc. IEEE Intl. Symp. on Circuits and Systems, May 1992, pp. 1113-1116.
14. J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong, “Provably Good Algorithms
for Performance-Driven Global Routing”, Proc. IEEE Intl. Symp. on Circuits and Systems, May
1992, pp. 2240-2243.
15. K. C. Chen, J. Cong, A. Kahng and P. Trajmar, “Graph Based FPGA Technology Mapping for
Delay Minimization”, Proc. IEEE Workshop on Field-Programmable Gate Arrays, March 1992,
pp. 77-81.
16. A. B. Kahng, “Random Structure of Error Surfaces: New Stochastic Learning Methods”, Invited
Paper, Proc. SPIE (Joint Conf. on Artificial Neural Networks: Science and Applications), 1710
(pt. 1, vol. 2) April 1992, pp. 768-779.
17. J. Cong, L. Hagen and A. B. Kahng, “Net Partitions Yield Better Module Partitions”, Proc. 29th
ACM/IEEE Design Automation Conf., June 1992, pp. 47-52 (nominated for Best Paper Award;
18 nominees out of 440 submissions).
18. L. Hagen, A. B. Kahng, F. Kurdahi and C. Ramachandran, “On the Intrinsic Rent Parameter and
New Spectra-Based Methods for Wireability Estimation”, Proc. European Design Automation
Conf., October 1992, pp. 202-208 (nominated for Best Paper Award; 6 nominees out of 335
submissions).
19. K. C. Chen, Y. Ding, J. Cong, A. Kahng and P. Trajmar, “An Improved Graph Based FPGA
Technology Mapping for Delay Minimization”, Proc. IEEE Intl. Conf. on Computer Design,
October 1992, pp. 154-158.
20. K. Boese and A. B. Kahng, “Zero-Skew Clock Routing Trees With Minimum Wirelength”, Proc.
IEEE 5th Intl. ASIC Conf., September 1992, pp. 1.1.1 - 1.1.5.