Curriculum Vitae - UCSD VLSI CAD Laboratory - UC San Diego

159. Y. Chen, P. Gupta and A. B. Kahng, “Performance-Impact Limited Area Fill Synthesis”, Proc.
ACM/IEEE Design Automation Conf., June 2003, pp. 22-27.
160. P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, “A Cost-Driven Lithographic Correction
Methodology Based on Off-the-Shelf Sizing Tools”, Proc. ACM/IEEE Design Automation Conf.,
June 2003, pp. 16-21.
161. H. Chen, C.-K. Cheng, N.-C. Chou, A. B. Kahng, J. F. MacDonald, P. Suaris, B. Yao and Z. Zhu,
“An Algebraic Multigrid Solver for Analytical Placement with Layout Based Clustering”, Proc.
ACM/IEEE Design Automation Conf., June 2003, pp. 794-799.
162. A. B. Kahng, I. I. Mandoiu, S. Reda, X. Xu, and A. Zelikovsky, “Design Flow Enhancements for
DNA Arrays”, Proc. IEEE Intl. Conf. on Computer Design, October 2003, pp. 116-123.
163. P. Gupta, A. B. Kahng, I. I. Mandoiu, and P. Sharma, “Layout-Aware Scan Chain Synthesis for
Improved Path Delay Fault Coverage”, Proc. IEEE/ACM Intl. Conference on Computer-Aided
Design, November 2003, pp. 754-759.
164. A. B. Kahng, I. I. Mandoiu, S. Reda, X. Xu, and A. Zelikovsky, “Evaluation of Placement
Techniques for DNA Probe Array Layout”, Proc. IEEE/ACM Intl. Conference on Computer-
Aided Design, November 2003, pp. 262-269.
165. H. Chen, C. K. Cheng, A. B. Kahng, I. I. Mandoiu, Q. Wang, and B. Yao, “The Y-Architecture
for On-Chip Interconnect: Analysis and Methodology”, Proc. IEEE/ACM Intl. Conference on
Computer-Aided Design, November 2003, pp. 13-19.
166. P. Gupta and A. B. Kahng, “Manufacturing-Aware Physical Design”, Proc. IEEE/ACM Intl.
Conference on Computer-Aided Design, November 2003, (embedded tutorial) pp. 681-687.
167. P. Gupta and A. B. Kahng, “Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive
Coupling”, Proc. IEEE Intl. Conf. on VLSI Design , Jan 2004, pp. 431-436.
168. H. Chen, C. K. Cheng, A. B. Kahng, M. Mori and Q. Wang, “Optimal Planning for Mesh-Based
Power Distribution”, Proc. Asia and South Pacific Design Automation Conf., Jan. 2004, pp. 444-
449.
169. A. B. Kahng and S. Reda, “Combinatorial Group Testing Methods for the BIST Diagnosis
Problem”, Proc. Asia and South Pacific Design Automation Conf., Jan. 2004, pp. 113-116.
170. P. Gupta, A.B. Kahng, Y. Kim, and D. Sylvester, “Investigation of Performance Metrics for
Interconnect Stack Architectures”, Proc. ACM International Workshop on System-Level
Interconnect Prediction, Feb. 2004, pp. 23-29.
171. A. B. Kahng, I. Markov and S. Reda, “Boosting: Min-Cut Placement with Improved Signal
Delay”, Proc. Design Automation and Testing in Europe, Feb. 2004, pp. 1098-1103.
172. A. B. Kahng, I. I. Mandoiu, Q. Wang, X. Xu, and A. Zelikovsky, “MultiProject Reticle
Floorplanning and Wafer Dicing”, Proc. ACM/IEEE Intl. Symp. on Physical Design, April 2004,
pp. 70-77.
173. A. B. Kahng, and Q. Wang, “Implementation and Extensibility of an Analytic Placer”, Proc.
ACM/IEEE Intl. Symp. on Physical Design, April 2004, pp. 18-25.
174. A. B. Kahng, I. L. Markov and S. Reda, “On Legalization of Row-Based Placements”, Proc.
ACM/IEEE GLSVLSI, April 2004, pp. 214-219.
175. A. B. Kahng and S. Reda, “Placement Feedback: A Concept and Method for Better Min-Cut
Placements”, Proc. ACM/IEEE Design Automation Conf., June 2004, pp.357-362.
176. P. Gupta, A. B. Kahng, P. Sharma and D. Sylvester, “Selective Gate-Length Biasing for Cost-
Effective Runtime Leakage Control”, Proc. ACM/IEEE Design Automation Conf., June 2004, pp.
327-330.
177. D. A. Antonelli, T. J. Dysart, D. Z. Chen, X. S. Hu, A. B. Kahng, P. M. Kogge and R. C. Murphy,
“Quantum-Dot Cellular Automata (QCA) Circuit Partitioning: Problem Modeling and Solutions”,
Proc. ACM/IEEE Design Automation Conf., June 2004, pp. 363-368.
178. L. Capodieci, P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, “Toward a Methodology for
Manufacturability Driven Design Rule Exploration”, Proc. ACM/IEEE Design Automation Conf.,
June 2004, pp. 311-316.