Curriculum Vitae - UCSD VLSI CAD Laboratory - UC San Diego

7. C. Albrecht, A. B. Kahng, I. I. Mandoiu and A. Z. Zelikovsky, “Multicommodity Flow
Algorithms for Buffered Global Routing”, Handbook of Approximation Algorithms and
Metaheuristics, T. E. Gonzalez (ed.), Chapman & Hall / CRC Press, 2007, pp. 80-1 - 80-18.
8. A. B. Kahng, I. I. Mandoiu, S. Reda, X. Xu, and A. Z. Zelikovsky, “Computer-Aided
Optimization of DNA Array Design and Manufacturing,” Design Automation Methods and Tools
for Microfluidics-Based Biochips, K. Chakrabarty and J. Zeng (eds.), Springer Verlag, 2006, pp.
235-269.
9. A. B. Kahng, S. Reda and Q. Wang, “APlace: A High Quality, Large-Scale Analytical Placer,”
Modern Circuit Placement: Best Practices and Results, J. Cong and G.-J. Nam (eds.), Springer,
2007, pp. 163 – 187.
10. (BOOK) B. P. Wong, A. Mittal, G. W. Starr, F. Zach, V. Moroz and A. Kahng, Nano-CMOS
Design for Manufacturability, Wiley-Interscience, 2008.
11. (BOOK) A. B. Kahng, J. Lienig, I. L. Markov and J. Hu, VLSI Physical Design: From Graph
Partitioning to Timing Closure, Springer, 2010.
Journal Papers
1. T. C. Hu and A. B. Kahng, “All Trees Are Graceful (but some are more graceful than others)”,
Applied Geometry and Discrete Mathematics 4 (1991), pp. 355-358.
2. A. B. Kahng and G. Robins, “Optimal Algorithms for Extracting Spatial Regularity in Images”,
Pattern Recognition Letters 12 (1991), pp. 757-764.
3. J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong, “Provably Good
Performance-Driven Global Routing”, IEEE Transactions on Computer-Aided Design 11(6), June
1992, pp. 739-752.
4. A. B. Kahng and G. Robins, “A New Class of Iterative Steiner Tree Heuristics with Good
Performance”, IEEE Transactions on Computer-Aided Design 11(7), July 1992, pp. 893-902.
5. L. Hagen and A. B. Kahng, “New Spectral Methods for Ratio Cut Partitioning and Clustering”,
IEEE Transactions on Computer-Aided Design 11(9), September 1992, pp. 1074-1085.
6. K. C. Chen, J. Cong, Y. Ding, A. B. Kahng and P. Trajmar, “DAG-MAP: Graph Based FPGA
Technology Mapping For Delay Optimization”, IEEE Design and Test, September 1992, pp. 7-
20.
7. T. C. Hu, A. B. Kahng and G. Robins, “Solution of the Discrete Plateau Problem”, Proc. National
Academy of Sciences 89(10), October 1992, pp. 9235-9236.
8. T. H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, “Zero Skew Clock Routing With
Minimum Wirelength”, IEEE Trans. on Circuits and Systems 39(11), November 1992, pp. 799-
814.
9. A. B. Kahng and G. Robins, “On Performance Bounds for a Class of Rectilinear Steiner Tree
Heuristics in Arbitrary Dimension”, IEEE Transactions on Computer-Aided Design 11(11),
November 1992, pp. 1462-1465.
10. J. Cong, A. B. Kahng and G. Robins, “Matching-Based Methods for High-Performance Clock
Routing”, IEEE Transactions on Computer-Aided Design 12(8), August 1993, pp. 1157-1169.
11. T. C. Hu, A. B. Kahng and G. Robins, “Optimal Robust Path Planning in General Environments”
IEEE Trans. on Robotics and Automation 9(6), December 1993, pp. 775-784.
12. L. Hagen, A. B. Kahng, F. Kurdahi and C. Ramachandran, “On the Intrinsic Rent Parameter and
New Spectra-Based Methods for Wireability Estimation”, IEEE Transactions on Computer-Aided
Design 13(1), January 1994, pp. 27-37.
13. K. D. Boese and A. B. Kahng, “Best-So-Far vs. Where-You-Are: Implications for Optimal Finite-
Time Annealing”, Systems and Control Letters 22, January 1994, pp. 71-78.
14. C. J. Alpert, J. Cong, A. B. Kahng, G. Robins and M. Sarrafzadeh, “On the Minimum Density
Interconnection Tree Problem”, VLSI Design 2(2) (1994), pp. 157-169.