Curriculum Vitae - UCSD VLSI CAD Laboratory - UC San Diego

82. A. B. Kahng, “IC Layout and Manufacturability: Critical Links and Design Flow Implications”,
Proc. IEEE Intl. Conf. on VLSI Design, Jan. 1999, pp. 100-105.
83. A. B. Kahng, G. Robins, A. Singh and A. Zelikovsky, “New and Exact Filling Algorithms for
Layout Density Control”, Proc. IEEE Intl. Conf. on VLSI Design, Jan. 1999, pp. 106-110.
84. A. B. Kahng, S. Muddu, E. Sarto, “Interconnect Optimization Strategies for High-Performance
VLSI Design”, Proc. IEEE Intl. Conf. on VLSI Design, Jan. 1999, pp. 464-469.
85. A. B. Kahng and S. Muddu, “Improved Effective Capacitance Computations for Use in Logic and
Layout Optimization”, Proc. IEEE Intl. Conf. on VLSI Design, Jan. 1999, pp. 578-582.
86. A. B. Kahng, G. Robins, A. Singh and A. Zelikovsky, “New Multilevel and Hierarchical
Algorithms for Layout Density Control”, Proc. Asia and South Pacific Design Automation Conf.,
Jan. 1999, pp. 221-224.
87. R. Baldick, A. B. Kahng, A. Kennings and I. L. Markov, “Function Smoothing with Applications
to VLSI Layout”, Proc. Asia and South Pacific Design Automation Conf., Jan. 1999, pp. 225-228.
Nominated for Best Paper Award.
88. A. B. Kahng, P. Tucker and A. Zelikovsky, “Optimization of Linear Placements for Wirelength
Minimization with Free Sites”, Proc. Asia and South Pacific Design Automation Conf., Jan. 1999,
pp. 241-244. Nominated for Best Paper Award.
89. A. E. Caldwell, A. B. Kahng and I. L. Markov, “Design and Implementation of the Fiduccia-
Mattheyses Heuristic for VLSI Netlist Partitioning”, Proc. Workshop on Algorithm Engineering
and Experimentation (ALENEX), Jan. 1999, pp. 177-193
90. P. Berman, A. B. Kahng, D. Vidhani, H. Wang and A. Zelikovsky, “Optimal Phase Conflict
Removal for Layout of Dark Field Alternating Phase Shifting Masks”, Proc. ACM Intl. Symp. on
Physical Design, April 1999, pp. 121-126.
91. A. E. Caldwell, A. B. Kahng and I. L. Markov, “Optimal Partitioners and End-Case Placers for
Standard-Cell Layout”, Proc. ACM Intl. Symp. on Physical Design, April 1999, pp. 90-96.
92. C. J. Alpert, A. E. Caldwell, A. B. Kahng and I. L. Markov, “Partitioning With Terminals: A
'New' Problem and New Benchmarks”, Proc. ACM Intl. Symp. on Physical Design, April 1999,
pp. 151-157.
93. A. B. Kahng and Y. C. Pati, “Subwavelength Optical Lithography: Challenges and Impact on
Physical Design”, Proc. ACM Intl. Symp. on Physical Design, April 1999, pp. 112-119.
94. A. E. Caldwell, A. B. Kahng, A. A. Kennings and I. L. Markov, “Hypergraph Partitioning for
VLSI CAD: Methodology for Reporting, and New Results”, Proc. ACM/IEEE Design
Automation Conf., June 1999, pp. 349-354.
95. A. E. Caldwell, A. B. Kahng and I. L. Markov, “Hypergraph Partitioning with Fixed Vertices”,
Proc. ACM/IEEE Design Automation Conf., June 1999, pp. 355-359.
96. A. E. Caldwell, H.-J. Choi, A. B. Kahng, S. Mantik, M. Potkonjak and G. Qu, “Effective Iterative
Techniques for Fingerprinting Design IP”, Proc. ACM/IEEE Design Automation Conf., June 1999,
pp. 843-848.
97. A. B. Kahng and Y. C. Pati, “Subwavelength Lithography and its Potential Impact on Design and
EDA”, Proc. ACM/IEEE Design Automation Conf., June 1999, pp. 799-804.
98. P. Berman, A. B. Kahng, D. Vidhani and A. Zelikovsky, “The T-Join Problem in Sparse Graphs:
Applications to Phase Assignment Problem in VLSI Mask Layout”, Proc. Workshop on
Algorithms and Data Structures (WADS), LNCS (vol. 1663), August 1999, pp. 25-36.
99. A. B. Kahng, S. Muddu and D. Vidhani, “Noise and Delay Uncertainty Studies for Coupled RC
Interconnects”, Proc. IEEE International ASIC/SOC Conference, September 1999, pp. 3-8.
100. Y. Chen, A. B. Kahng, G. Qu and A. Zelikovsky, “The Associative-Skew Clock Routing
Problem”, Proc. IEEE/ACM Intl. Conference on Computer-Aided Design, November 1999, pp.
168-172.
101. A. B. Kahng, D. Kirovski, S. Mantik, M. Potkonjak and J. L. Wong, “Copy Detection for
Intellectual Property Protection of VLSI Design”, Proc. IEEE/ACM Intl. Conference on
Computer-Aided Design, November 1999, pp. 600-604.