Curriculum Vitae - UCSD VLSI CAD Laboratory - UC San Diego

122. C. K. Cheng, A. B. Kahng and B. Liu, “Interconnect Implications of Growth-Based Structural
Models for VLSI Circuits”, Proc. ACM International Workshop on System-Level Interconnect
Prediction, April 2001, pp. 99-106.
123. K. D. Boese, A. B. Kahng and S. Mantik, “On the Relevance of Wire Load Models”, Proc. ACM
International Workshop on System-Level Interconnect Prediction, April 2001, pp. 91-98.
124. C. J. Alpert, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar, A. J.
Sullivan and P. Villarrubia, “Buffered Steiner Trees for Difficult Instances”, Proc. ACM/IEEE
Intl. Symp. on Physical Design, April 2001, pp. 4-9.
125. F. Dragan, A. B. Kahng, I. Mandoiu, S. Muddu and A. Zelikovsky, “Practical Approximation
Algorithms for Separable Packing Linear Programs”, Proc. 7th International Workshop on
Algorithms and Data Structures, August 2001, pp. 325-337.
126. C. Albrecht, A. B. Kahng, B. Liu, I. Mandoiu and A. Zelikovsky, “On the Skew-Bounded
Minimum Buffer Routing Tree Problem”, Proc. The Tenth Workshop on Synthesis And System
Integration of Mixed Technologies, October 2001, pp. 250-256.
127. A. B. Kahng, R. Kastner, S. Mantik, M. Sarrafzadeh, and X. Yang, “Studies of Timing Structural
Properties for Early Evaluation of Circuit Design”, Proc. The Tenth Workshop on Synthesis and
System Integration of Mixed Technologies, October 2001, pp. 285-292.
128. C. Alpert, A. B. Kahng, B. Liu, I. Mandoiu and A. Zelikovsky, “Minimum-Buffered Routing of
Non-Critical Nets for Slew Rate and Reliability Control”, Proc. IEEE-ACM Intl. Conf. on
Computer-Aided Design, November 2001, pp. 408-415.
129. C. Albrecht, A. B. Kahng, I. Mandoiu and A. Zelikovsky, “Floorplan Evaluation with Timing-
Driven Global Wireplanning, Pin Assignment, and Buffer/Wire Sizing”, Proc. Intl. Conf. on
VLSI Design/ASPDAC, January 2002, pp. 580-587. Best Paper Award out of 269 submissions.
130. A. Kahng and S. Mantik, “Measurement of Inherent Noise in EDA Tools”, Proc. International
Symposium on Quality in Electronic Design, March 2002, pp. 206-211.
131. A. Kahng and G. Smith, “A New Design Cost Model for 2001 ITRS”, Proc. International
Symposium on Quality Electronic Design, March 2002, pp. 190-193.
132. Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, “Monte-Carlo Methods for Chemical-
Mechanical Planarization on Multiple-Layer and Dual-Material Models”, Proc. SPIE Conference
on Design and Process Integration for Microelectronic Manufacturing, Santa Clara, March 2002,
pp. 421-432.
133. A. B. Kahng, “Design-Manufacturing Integration and Shared “Brick Walls” “, Proc. SPIE
Conference on Design and Process Integration for Microelectronic Manufacturing, Santa Clara,
March 2002, pp. 390-400.
134. Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, “Closing the Smoothness and Uniformity
Gap in Area Fill Synthesis”, Proc. ACM/IEEE Intl. Symp. on Physical Design, April 2002, pp.
137-142.
135. A. B. Kahng, S. Mantik and I. L. Markov, “Min-Max Placements for Large-Scale Timing
Optimization”, Proc. ACM/IEEE Intl. Symp. on Physical Design, April 2002, pp. 143-148.
136. A. B. Kahng, “A Roadmap and Vision for Physical Design”, Proc. ACM/IEEE Intl. Symp. on
Physical Design, April 2002, pp. 112-117.
137. C. Bandela, Y. Chen, A. B. Kahng, I. I. Mandoiu and A. Zelikovsky, “Auctions with Buyer
Preferences”, Information Systems: The E-Business Challenge - Proc. 17th IFIP World
Computer Congress, Kluwer Academic Publishers, 2002, pp. 221-238.
138. Y. Cao, P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, “Design Sensitivities to Variability:
Extrapolation and Assessments in Nanometer VLSI”, Proc. IEEE ASIC/SoC Conference,
September 2002, pp. 411-415.
139. A. B. Kahng, I. I. Mandoiu, P. A. Pevzner, S. Reda, and A. A. Zelikovsky, “Border Length
Minimization in DNA Array Design”, Proc. 2nd Workshop on Algorithms in Bioinformatics
(WABI), September 2002, pp. 435-448.