Introduction to QuartusÂ® II

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CHAPTER 5: PLACE & ROUTE PERFORMING A FULL INCREMENTAL COMPILATION Performing a Full Incremental Compilation You can perform a full incremental compilation to preserve design performance and save compilation time by reusing previous compilation results and ensuring that only the parts of the design that have been modified need to be recompiled. Performing a full incremental compilation is part of the top-down incremental compilation flow. For more information, refer to “Top-Down Incremental Compilation Flow” on page 38 in Chapter 1, “Design Flow.” You can perform an incremental synthesis only, or you can perform a full incremental compilation. For more information about performing only an incremental synthesis, refer to “Performing Incremental Synthesis” on page 94 in Chapter 4, “Synthesis.” The following steps describe the basic flow for performing a full incremental compilation: 1. Perform Analysis & Elaboration. 2. Specify one or more entities of the project as partitions. Refer to “Assigning Design Partitions” on page 70 in Chapter 3, “Constraint Entry.” 3. Select Full Incremental compilation as the Incremental compilation mode. 4. Set the appropriate Netlist Type for the partitions. To preserve compilation and placement results, set the Netlist Type for the partitions to Post-Fit. 5. Assign each partition to a physical location on the device by using the Timing Closure floorplan and LogicLock assignments. Refer to “Using LogicLock Regions in Top-Down Incremental Compilation Flows” on page 126 in Chapter 6, “Block-Based Design.” 6. Perform a setup compilation, which is a full compilation of the design. 7. Make changes to the design or design settings, as needed. 8. Compile again. Only the partitions that have changed will be compiled. ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 99
CHAPTER 5: PLACE & ROUTE ANALYZING FITTING RESULTS f For Information About Using Quartus II incremental compilation Refer To Quartus II Incremental Compilation chapter in volume 1 of the Quartus II Handbook “About Incremental Compilation” in Quartus II Help Analyzing Fitting Results The Quartus II software offers several tools to help you analyze the results of compilation and fitting. The Messages window and Report window provide fitting results information. The Timing Closure floorplan and Chip Planner allow you to view fitting results and make adjustments, if necessary. In addition, the Design Assistant helps you check the reliability of a design based on a set of design rules. Using the Messages Window to View Fitting Results The Processing tab of the Messages window and the Messages section of the Report window or Report File display the messages generated from the most recent compilation or simulation. Figure 3 shows the Messages window. 100 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
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Introduction to Quartus ® II Versi
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Introduction to Quartus II Altera,
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TABLE OF CONTENTS Assigning Design
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TABLE OF CONTENTS Using Incremental
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Preface The Altera ® Quartus ® II
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DOCUMENTATION CONVENTIONS Terminolo
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CHAPTER 1: DESIGN FLOW INTRODUCTION
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CHAPTER 1: DESIGN FLOW GRAPHICAL US
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CHAPTER 1: DESIGN FLOW EDA TOOL DES
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CHAPTER 1: DESIGN FLOW EDA TOOL DES
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CHAPTER 1: DESIGN FLOW COMMAND-LINE
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CHAPTER 1: DESIGN FLOW DESIGN METHO
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Chapter Two Design Entry What’s i
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CHAPTER 2: DESIGN ENTRY CREATING A
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CHAPTER 2: DESIGN ENTRY CREATING A
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Page 59 and 60: CHAPTER 2: DESIGN ENTRY USING ALTER
Page 67 and 68: Chapter Three Constraint Entry What
Page 69 and 70: CHAPTER 3: CONSTRAINT ENTRY INTRODU
Page 71 and 72: CHAPTER 3: CONSTRAINT ENTRY USING T
Page 73 and 74: CHAPTER 3: CONSTRAINT ENTRY ASSIGNI
Page 75 and 76: CHAPTER 3: CONSTRAINT ENTRY ASSIGNI
Page 77 and 78: CHAPTER 3: CONSTRAINT ENTRY VERIFYI
Page 79 and 80: CHAPTER 4: SYNTHESIS INTRODUCTION I
Page 81 and 82: CHAPTER 4: SYNTHESIS USING QUARTUS
Page 83 and 84: CHAPTER 4: SYNTHESIS USING OTHER ED
Page 85 and 86: CHAPTER 4: SYNTHESIS USING OTHER ED
Page 87 and 88: CHAPTER 4: SYNTHESIS CONTROLLING AN
Page 89 and 90: CHAPTER 4: SYNTHESIS CONTROLLING AN
Page 91 and 92: CHAPTER 4: SYNTHESIS USING THE DESI
Page 97 and 98: CHAPTER 4: SYNTHESIS PERFORMING INC
Page 99 and 100: Chapter Five Place & Route What’s
Page 101: CHAPTER 5: PLACE & ROUTE INTRODUCTI
Page 105 and 106: CHAPTER 5: PLACE & ROUTE ANALYZING
Page 111 and 112: CHAPTER 5: PLACE & ROUTE OPTIMIZING
Page 113 and 114: . CHAPTER 5: PLACE & ROUTE OPTIMIZI
Page 121 and 122: CHAPTER 5: PLACE & ROUTE PRESERVING
Page 123 and 124: Chapter Six Block-Based Design What
Page 125 and 126: CHAPTER 6: BLOCK-BASED DESIGN USING
Page 131 and 132: CHAPTER 6: BLOCK-BASED DESIGN EXPOR
Page 133 and 134: Chapter Seven Simulation What’s i
Page 135 and 136: CHAPTER 7: SIMULATION SIMULATING DE
Page 147 and 148: Chapter Eight Timing Analysis What
Page 149 and 150: CHAPTER 8: TIMING ANALYSIS CHOOSING
Page 151 and 152: CHAPTER 8: TIMING ANALYSIS TIMEQUES
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CHAPTER 8: TIMING ANALYSIS CLASSIC
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CHAPTER 8: TIMING ANALYSIS PERFORMI
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CHAPTER 9: TIMING CLOSURE INTRODUCT
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CHAPTER 9: TIMING CLOSURE USING THE
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CHAPTER 9: TIMING CLOSURE USING THE
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CHAPTER 9: TIMING CLOSURE USING NET
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CHAPTER 9: TIMING CLOSURE USING LOG
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CHAPTER 9: TIMING CLOSURE USING LOG
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CHAPTER 9: TIMING CLOSURE USING INC
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CHAPTER 10: POWER ANALYSIS INTRODUC
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CHAPTER 10: POWER ANALYSIS SPECIFYI
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CHAPTER 10: POWER ANALYSIS USING TH
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Chapter Eleven Programming & Config
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CHAPTER 11: PROGRAMMING & CONFIGURA
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Chapter Twelve Debugging What’s i
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CHAPTER 12: DEBUGGING USING THE SIG
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CHAPTER 12: DEBUGGING USING AN EXTE
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CHAPTER 12: DEBUGGING USING SIGNALP
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CHAPTER 12: DEBUGGING USING THE IN-
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CHAPTER 12: DEBUGGING USING THE CHI
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CHAPTER 13: ENGINEERING CHANGE MANA
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CHAPTER 14: FORMAL VERIFICATION INT
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CHAPTER 14: FORMAL VERIFICATION USI
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CHAPTER 14: FORMAL VERIFICATION SPE
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CHAPTER 15: SYSTEM-LEVEL DESIGN INT
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CHAPTER 15: SYSTEM-LEVEL DESIGN CRE
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CHAPTER 16: INSTALLATION, LICENSING
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CHAPTER 17: DOCUMENTATION & OTHER R
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INDEX Create/Update > Create/Update
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INDEX using with clear box methodol
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INDEX SOFs 189, 193, 194 Software B
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Copyright © 2006 Altera Corporatio
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Introduction to QuartusÂ® II

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