Introduction to Quartus® II

CHAPTER 1: DESIGN FLOW
DESIGN METHODOLOGIES & DESIGN PLANNING
Top-Down Incremental Compilation
Flow
Incremental compilation allows you to preserve design performance and
save compilation time by reusing previous compilation results and ensuring
that only the parts of the design that have been modified are recompiled. The
top-down incremental compilation flow can help you to improve timing by
allowing you to change the placement of only the critical elements of the
design while processing the other design partitions, or allowing you to
specify the placement only for designated portions of the design so that the
Compiler can automatically optimize the rest of the design.
In the incremental compilation flow, you assign an instance of a design
entity to a design partition. You then assign the partitions to a physical
location on the device by using the Timing Closure floorplan or Chip
Planner, and the LogicLock feature, and perform a full compilation of the
design. During compilation, the Compiler saves synthesis and fitting results
in the project database. After the first compilation, if you make additional
changes to the design, only the partitions that have changed require
recompilation.
When you are finished making design changes you can choose to perform
only incremental synthesis, which can reduce compilation time, or a full
incremental compilation, which can preserve performance in addition to
significantly reducing compilation time. In either case, the Quartus II
software merges all partitions together for the chosen task.
Because incremental compilation prevents the Compiler from optimizing
across design partition boundaries, the Compiler may not be able to perform
as many optimizations for area and timing as would be possible with regular
compilation. To obtain best results for area and timing, register the inputs
and outputs of design partitions, try to keep the number of design partitions
to a reasonable amount, avoid having too many critical paths that go beyond
partition boundaries, and avoid having partitions that are too small, such as
smaller than 1000 logic elements or Adaptive Logic Modules (ALMs).
For more information on assigning partitions and other stages of the
incremental compilation flow, see the following sections:
■ “Assigning Design Partitions” on page 70 in Chapter 3, “Constraint
Entry.”
■ “Performing Incremental Synthesis” on page 94 in Chapter 4,
“Synthesis.”
38 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION