Introduction to Quartus® II

CHAPTER 1: DESIGN FLOW
DESIGN METHODOLOGIES & DESIGN PLANNING
■ “Performing a Full Incremental Compilation” on page 99 in Chapter 5,
“Place & Route.”
■ “Using LogicLock Regions in Top-Down Incremental Compilation
Flows” on page 126 in Chapter 6, “Block-Based Design.”
■ “Using Incremental Compilation to Achieve Timing Closure” on page
179 in Chapter 9, “Timing Closure.”
■ “Using the SignalTap II Logic Analyzer with Incremental Compilation”
on page 209 in Chapter 12, “Debugging.”
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For Information About
Using Quartus II incremental
compilation and incremental synthesis
and the incremental compilation flow
Refer To
Quartus II Incremental Compilation chapter
in volume 1 of the Quartus II Handbook
“About Incremental Compilation” and
“About Incremental Synthesis” in Quartus II
Help
Bottom-Up Incremental Compilation
Flow
In the bottom-up incremental compilation design flow, you can design and
optimize each module independently, integrate all optimized modules in a
top-level design, and then verify the overall design. Each module has a
separate netlist, which can then be incorporated after synthesis and
optimization into the top-level design. Each module in the top-level design
does not affect the performance of the other modules. The general
block-based design flow concepts can be used in modular, hierarchical,
incremental, and team-based design flows.
You can use EDA design entry and synthesis tools in the block-based design
flow to design and synthesize individual modules, and then incorporate the
modules into a top-level design in the Quartus II software, or completely
design and synthesize a block-based design in EDA design entry and
synthesis tools. For more information on the block-based design flow, refer
to “Chapter 6: Block-Based Design” on page 120.
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 39