Introduction to QuartusÂ® II

More documents

Recommendations

Info

CHAPTER 1: DESIGN FLOW GRAPHICAL USER INTERFACE DESIGN FLOW Figure 5. Quartus II and MAX+PLUS II Quick Menus Quartus II Quick Menu MAX+PLUS II Quick Menu ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 15
CHAPTER 1: DESIGN FLOW GRAPHICAL USER INTERFACE DESIGN FLOW f For Information About Using the Quartus II design flow for MAX+PLUS II users Customizing the user interface Using the MAX+PLUS II look and feel Refer To The Quartus II Design Flow for MAX+PLUS II Users chapter in volume 1 of the Quartus II Handbook “About Customizing the User Interface” in Quartus II Help “MAX+PLUS II Quick Start Guide for the Quartus II Software” and “List of MAX+PLUS II Commands” in Quartus II Help The following steps describe the basic design flow for using the Quartus II graphical user interface: 1. To create a new project and specify a target device or device family, on the File menu, click New Project Wizard. 2. Use the Text Editor to create a Verilog HDL, VHDL, or Altera Hardware Description Language (AHDL) design. Use the Block Editor to create a block diagram with symbols that represent other design files, or to create a schematic. 3. Use the MegaWizard ® Plug-In Manager to generate custom variations of megafunctions and IP functions to instantiate in your design, or create a system-level design by using SOPC Builder or DSP Builder. 4. Specify any initial design constraints using the Assignment Editor, the Pin Planner, the Settings dialog box, the Floorplan Editor, or the Design Partitions window. 5. (Optional) Perform an early timing estimate to generate early estimates of timing results before fitting. 6. Synthesize the design with Analysis & Synthesis. 7. (Optional) If your design contains partitions and you are not performing a full compilation, merge the partitions with partition merge. 8. (Optional) Generate a functional simulation netlist for your design and perform a functional simulation with the Simulator. 9. Place and route the design with the Fitter. 16 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
Page 1 and 2: Introduction to Quartus ® II Versi
Page 3 and 4: Introduction to Quartus II Altera,
Page 5 and 6: TABLE OF CONTENTS Assigning Design
Page 7 and 8: TABLE OF CONTENTS Using Incremental
Page 9 and 10: Preface The Altera ® Quartus ® II
Page 11 and 12: DOCUMENTATION CONVENTIONS Terminolo
Page 13 and 14: CHAPTER 1: DESIGN FLOW INTRODUCTION
Page 15 and 16: CHAPTER 1: DESIGN FLOW GRAPHICAL US
Page 17: CHAPTER 1: DESIGN FLOW GRAPHICAL US
Page 21 and 22: CHAPTER 1: DESIGN FLOW EDA TOOL DES
Page 23 and 24: CHAPTER 1: DESIGN FLOW EDA TOOL DES
Page 25 and 26: CHAPTER 1: DESIGN FLOW COMMAND-LINE
Page 39 and 40: CHAPTER 1: DESIGN FLOW DESIGN METHO
Page 45 and 46: Chapter Two Design Entry What’s i
Page 47 and 48: CHAPTER 2: DESIGN ENTRY CREATING A
Page 59 and 60: CHAPTER 2: DESIGN ENTRY USING ALTER
Page 67 and 68: Chapter Three Constraint Entry What
Page 69 and 70:
CHAPTER 3: CONSTRAINT ENTRY INTRODU
Page 71 and 72:
CHAPTER 3: CONSTRAINT ENTRY USING T
Page 73 and 74:
CHAPTER 3: CONSTRAINT ENTRY ASSIGNI
Page 75 and 76:
CHAPTER 3: CONSTRAINT ENTRY ASSIGNI
Page 77 and 78:
CHAPTER 3: CONSTRAINT ENTRY VERIFYI
Page 79 and 80:
CHAPTER 4: SYNTHESIS INTRODUCTION I
Page 81 and 82:
CHAPTER 4: SYNTHESIS USING QUARTUS
Page 83 and 84:
CHAPTER 4: SYNTHESIS USING OTHER ED
Page 85 and 86:
CHAPTER 4: SYNTHESIS USING OTHER ED
Page 87 and 88:
CHAPTER 4: SYNTHESIS CONTROLLING AN
Page 89 and 90:
CHAPTER 4: SYNTHESIS CONTROLLING AN
Page 91 and 92:
CHAPTER 4: SYNTHESIS USING THE DESI
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
CHAPTER 4: SYNTHESIS PERFORMING INC
Page 99 and 100:
Chapter Five Place & Route What’s
Page 101 and 102:
CHAPTER 5: PLACE & ROUTE INTRODUCTI
Page 103 and 104:
CHAPTER 5: PLACE & ROUTE ANALYZING
Page 105 and 106:
Page 107 and 108:
Page 109 and 110:
Page 111 and 112:
CHAPTER 5: PLACE & ROUTE OPTIMIZING
Page 113 and 114:
. CHAPTER 5: PLACE & ROUTE OPTIMIZI
Page 115 and 116:
Page 117 and 118:
Page 119 and 120:
Page 121 and 122:
CHAPTER 5: PLACE & ROUTE PRESERVING
Page 123 and 124:
Chapter Six Block-Based Design What
Page 125 and 126:
CHAPTER 6: BLOCK-BASED DESIGN USING
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
CHAPTER 6: BLOCK-BASED DESIGN EXPOR
Page 133 and 134:
Chapter Seven Simulation What’s i
Page 135 and 136:
CHAPTER 7: SIMULATION SIMULATING DE
Page 137 and 138:
Page 139 and 140:
Page 141 and 142:
Page 143 and 144:
Page 145 and 146:
Page 147 and 148:
Chapter Eight Timing Analysis What
Page 149 and 150:
CHAPTER 8: TIMING ANALYSIS CHOOSING
Page 151 and 152:
CHAPTER 8: TIMING ANALYSIS TIMEQUES
Page 153 and 154:
CHAPTER 8: TIMING ANALYSIS CLASSIC
Page 155 and 156:
Page 157 and 158:
Page 159 and 160:
CHAPTER 8: TIMING ANALYSIS PERFORMI
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
Page 169 and 170:
Page 171 and 172:
CHAPTER 9: TIMING CLOSURE INTRODUCT
Page 173 and 174:
CHAPTER 9: TIMING CLOSURE USING THE
Page 175 and 176:
CHAPTER 9: TIMING CLOSURE USING THE
Page 177 and 178:
CHAPTER 9: TIMING CLOSURE USING NET
Page 179 and 180:
CHAPTER 9: TIMING CLOSURE USING LOG
Page 181 and 182:
CHAPTER 9: TIMING CLOSURE USING LOG
Page 183 and 184:
CHAPTER 9: TIMING CLOSURE USING INC
Page 185 and 186:
CHAPTER 10: POWER ANALYSIS INTRODUC
Page 187 and 188:
CHAPTER 10: POWER ANALYSIS SPECIFYI
Page 189 and 190:
CHAPTER 10: POWER ANALYSIS USING TH
Page 191 and 192:
Chapter Eleven Programming & Config
Page 193 and 194:
CHAPTER 11: PROGRAMMING & CONFIGURA
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
Chapter Twelve Debugging What’s i
Page 207 and 208:
CHAPTER 12: DEBUGGING USING THE SIG
Page 209 and 210:
Page 211 and 212:
Page 213 and 214:
Page 215 and 216:
CHAPTER 12: DEBUGGING USING AN EXTE
Page 217 and 218:
CHAPTER 12: DEBUGGING USING SIGNALP
Page 219 and 220:
CHAPTER 12: DEBUGGING USING THE IN-
Page 221 and 222:
CHAPTER 12: DEBUGGING USING THE CHI
Page 223 and 224:
CHAPTER 13: ENGINEERING CHANGE MANA
Page 225 and 226:
Page 227 and 228:
Page 229 and 230:
Page 231 and 232:
Page 233 and 234:
CHAPTER 14: FORMAL VERIFICATION INT
Page 235 and 236:
CHAPTER 14: FORMAL VERIFICATION USI
Page 237 and 238:
CHAPTER 14: FORMAL VERIFICATION SPE
Page 239 and 240:
CHAPTER 15: SYSTEM-LEVEL DESIGN INT
Page 241 and 242:
CHAPTER 15: SYSTEM-LEVEL DESIGN CRE
Page 243 and 244:
Page 245 and 246:
Page 247 and 248:
CHAPTER 16: INSTALLATION, LICENSING
Page 249 and 250:
Page 251 and 252:
Page 253 and 254:
CHAPTER 17: DOCUMENTATION & OTHER R
Page 255 and 256:
Page 257 and 258:
Page 259 and 260:
INDEX Create/Update > Create/Update
Page 261 and 262:
INDEX using with clear box methodol
Page 263 and 264:
INDEX SOFs 189, 193, 194 Software B
Page 266:
Copyright © 2006 Altera Corporatio
show all

Introduction to QuartusÂ® II

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?