Introduction to Quartus® II

CHAPTER 9: TIMING CLOSURE
USING LOGICLOCK REGIONS TO ACHIEVE TIMING CLOSURE
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Perform physical synthesis for combinational logic: Directs the
Quartus II software to try to increase performance by performing
physical synthesis optimizations on combinational logic during fitting.
Perform register duplication: Directs the Quartus II software to
increase performance by using register duplication to perform physical
synthesis optimizations on registers during fitting.
Perform register retiming: Directs the Quartus II software to increase
performance by using register retiming to perform physical synthesis
optimizations on registers during fitting.
Physical synthesis effort: Specifies the level of effort used by the
Quartus II software when performing physical synthesis (Normal,
Extra, and Fast).
The Quartus II software cannot perform these netlist optimizations for
fitting and physical synthesis on a back-annotated design. In addition, if you
use one or more of these netlist optimizations on a design, and then backannotate
the design, you must generate a Verilog Quartus Mapping
File (.vqm) if you wish to save the results. The Verilog Quartus Mapping File
must be used in place of the original design source code in future
compilations.
f
For Information About
Achieving timing closure using netlist
optimizations
Refer To
Netlist Optimizations and Physical
Synthesis chapter in volume 2 of the
Quartus II Handbook
Using LogicLock Regions to Achieve
Timing Closure
You can use LogicLock regions to achieve timing closure by analyzing the
design in the Timing Closure floorplan, and then constraining critical logic
in LogicLock regions. LogicLock regions are generally hierarchical, giving
you more control over the placement and performance of modules or groups
of modules. You can use the LogicLock feature on individual nodes, for
instance, by assigning the nodes along the critical path to a LogicLock
region.
176 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION