A Symbolic Analysis of Relay and Switching Circuits

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15 therefore necessary to manipulate the expression into the form in which the least numb~r of letters appear. The theorems ~iven above are always sufficient to do this. A ].1ttle practice in the manipulation of these s;rm1:o1s is 811 that is required. Fortunately most of the theorems are exactly the same as those of numerical al~eora--the associative, commutative, and distribut1ve laws of algebra hold here. The writer has found theorems 3, 6, 9,14, 15, 16a, 17, and 18 to be especlally useful in the simplification of complex axpres sian s. AS a n exampl e of the 81mp11 fica tion of expressions consider the circuit shoWn in Fi~. 5. ~.-. 5' v y _-.....--0 0---0 • ~ WI Fi Q;. 5 • x o z' ...... '0 Z The hind'3rance function X ab for this circllit will be: X ab = W+\\II(X+Y) + (X+~HS+W'+e)(~'+Y+S'V) , ~ "i\[ = ~+X+Y+(X+~)(S+l+g)(gl+Y+stV) v = W+X+y+g(~'+S'V) lthesa reductions walee made \'V1"tth 17b using first ~N, then X and
16 y as the "XU of 17b. }IO\iV multiplying out: X ab =W + X + Y + gel + ~~SIV : W + x + y + ~SIV The circuit corresponding to this expression is shown in Fig. 6. Note the large reduction in the number of elements. w X· Y a _.-lIDO ViO----00 DlO--_.n.o a----.....--a z Fig. 6 It is convenient in drawing circuit~ to label a relay With the same letter as the hinderance of make contacts of the relay. Thus if a relay is conneoted to e source of voltBQ:6 through a network whose hlnder8nce function is X, the relay and any make contecta on-it would be labeled X. Break aontects would be labeled XI. This assumes tr~t the relay operates instarltlY and that the make oontacts close end the break contacts open s1multaneousl.. y. Cases in which there 1s 8 time delay will be treated later. It is also possible to use the analogy between Booleian algebra and relay circu1~s in th9 opposite direction, i.e., to represent logical relations by
Page 1 and 2: A SYl~:BOLIC OF Al~ALYSIS by Claude
Page 3 and 4: ACKNOvVLEDG1ffiNT The author is ind
Page 5 and 6: 2 COL~ac:s be ~ound. Although a sol
Page 7 and 8: • 4 II ~eries-parallel Two Termin
Page 9 and 10: • 6 3. a~ 0 + 0 = 0 A closed ~irc
Page 11 and 12: 8 equals 1 .. If X is the }1-ind-=J
Page 13 and 14: 10 Ole to thi s analogy any theorem
Page 15 and 16: 12 first note the following equatio
Page 17: l~ be obtained by replacin~ each va
Page 21 and 22: 18 III Multi-terminal end Non-aerie
Page 23 and 24: 20 The wye to delta tran sformation
Page 25 and 26: 22 Fig. 12 'The hinderance function
Page 27 and 28: This 8~a1n gives for the hinderance
Page 29 and 30: 26 I I I 1 X 12 X 13 • • •
Page 31 and 32: 28 Xi matrix the oroduct of the ele
Page 33 and 34: 30 50m~~~mes a relay X 1s to operat
Page 35 and 36: 32 where (~) : nl/k Hn-k) ~ is the
Page 37 and 38: This will be proved by mathematical
Page 39 and 40: 36 Dual l{et\vorks. The ne~et1ve of
Page 41 and 42: 38 In a eonstant-voltage relay syst
Page 43 and 44: identically the same. Thus XY + XZ
Page 45 and 46: 42 zero if either factor is zero, w
Page 47 and 48: varia "bles of Fig. 26, the termina
Page 49 and 50: 46 the circuits are- as shown in Fi
Page 51 and 52: !8 a time delay relB;T of sona so r
Page 53 and 54: 50- on the in genu~..ty 0 f the de
Page 55 and 56: 52 A Selective Circuit A relay 1:\
Page 57 and 58: 54 Zl z .~ "f'l, +--........~---" A
Page 59 and 60: 56 11Vhen z has opersted the lock u
Page 61 and 62: 58 A Vote Counting Circuit A circui
Page 63 and 64: 60 starting from the right, So is o
Page 65 and 66: 62 A Factor Table Machine A machine
Page 67 and 68: ep11ssent1ng the numbe'!' being con
Page 69 and 70:
66 Usin~ the method of factorj.ng o
Page 71 and 72:
This design requires tnat t~e prime
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A Symbolic Analysis of Relay and Switching Circuits

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