A Symbolic Analysis of Relay and Switching Circuits

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,. f' ; \ ~~i ~\. .... TABLE OF CO~TTENTS page Introduction; Types of Problems - - - - - - ~ - - 1 II series-Parallel Two-Terminal Circuits Fundamental Definitions and Postulates - - - - Theorems - - - - - - - - - - - - - - - - - - - - - 6 Analogue With the calculus of Propositions - - - 8 III Multl- Irarminal and Non-Saries-Parallel Networks - - -18 Equivalence of n-Term1nel Networks ~ - - - ~ - - - - 18 star-Ivlash and Delts-'Nye Transformations - - - - - - 19 Hinderance Function of a Non-Sarles-Parallel Network 21 S1roultanaous Equations - .. - _. - - - - •. - - - - - 2~ Matrix Methods - - - - - - - - - - - - - - - - - 25 Special Types of Relays and S~itohes ... - 28 \ IV ~~thas1s of Networks - - - - - - - - - - - - - - - 31 General Theorems on Networks and Functions - - - - 31 Due 1 ,N etworks - - - - - - - - - - - - - - - - - - - 36 synthesis of the Gapersl Symmetric Function - - - - 39 Equations from Given Operating Characteristics - - - 47 v Illustrative Examples - - - - A selective Circuit - An Electric Comb1nat1.on Lock - - - - - - - - - - -51 - - - 52 55 A Vote COU~t1ng C1rcu1 t 58 An Adder to the Ba sa Two 59 A Factor References 69
ACKNOvVLEDG1ffiNT The author is indebted to PrOfeSSOI' F. L. Hitchcock, who supervised the thesis, for helpful criticism and advice. ,
Page 1: A SYl~:BOLIC OF Al~ALYSIS by Claude
Page 5 and 6: 2 COL~ac:s be ~ound. Although a sol
Page 7 and 8: • 4 II ~eries-parallel Two Termin
Page 9 and 10: • 6 3. a~ 0 + 0 = 0 A closed ~irc
Page 11 and 12: 8 equals 1 .. If X is the }1-ind-=J
Page 13 and 14: 10 Ole to thi s analogy any theorem
Page 15 and 16: 12 first note the following equatio
Page 17 and 18: l~ be obtained by replacin~ each va
Page 19 and 20: 16 y as the "XU of 17b. }IO\iV mult
Page 21 and 22: 18 III Multi-terminal end Non-aerie
Page 23 and 24: 20 The wye to delta tran sformation
Page 25 and 26: 22 Fig. 12 'The hinderance function
Page 27 and 28: This 8~a1n gives for the hinderance
Page 29 and 30: 26 I I I 1 X 12 X 13 • • •
Page 31 and 32: 28 Xi matrix the oroduct of the ele
Page 33 and 34: 30 50m~~~mes a relay X 1s to operat
Page 35 and 36: 32 where (~) : nl/k Hn-k) ~ is the
Page 37 and 38: This will be proved by mathematical
Page 39 and 40: 36 Dual l{et\vorks. The ne~et1ve of
Page 41 and 42: 38 In a eonstant-voltage relay syst
Page 43 and 44: identically the same. Thus XY + XZ
Page 45 and 46: 42 zero if either factor is zero, w
Page 47 and 48: varia "bles of Fig. 26, the termina
Page 49 and 50: 46 the circuits are- as shown in Fi
Page 51 and 52: !8 a time delay relB;T of sona so r
Page 53 and 54:
50- on the in genu~..ty 0 f the de
Page 55 and 56:
52 A Selective Circuit A relay 1:\
Page 57 and 58:
54 Zl z .~ "f'l, +--........~---" A
Page 59 and 60:
56 11Vhen z has opersted the lock u
Page 61 and 62:
58 A Vote Counting Circuit A circui
Page 63 and 64:
60 starting from the right, So is o
Page 65 and 66:
62 A Factor Table Machine A machine
Page 67 and 68:
ep11ssent1ng the numbe'!' being con
Page 69 and 70:
66 Usin~ the method of factorj.ng o
Page 71 and 72:
This design requires tnat t~e prime
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A Symbolic Analysis of Relay and Switching Circuits

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