A Symbolic Analysis of Relay and Switching Circuits

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• 3 and for certain types of functions it is 903sible to find the simplest circuit containing any type of connection. In the analysis problem the equations re~resenting the given circuit are written and may then be interpreted in terms of the ogerating characteristics of the circuit. It is alGo possible with the calculus to obtain any number of circuits equivalent to a given circuit. phraseology will be borrowed frJm ordinary network theory for con06pts in switching circuits that are rough~y aL~logous to those of iffipedencJ networks.
• 4 II ~eries-parallel Two Terminal Jircuits Funda~ental Definitions and Postulates. Tve sha 11 limit our treatrn8nt to circuits containing only relay contacts and switches, and therefore at any given time the circui t between any tVifo termi nals must be either open (infinite impedance) or Closed (zero impedance). Let us associate a symbol X or more ao simply X, with the terminals a ana b. This variable, a. function of time, lNill be called the hinderance of the two terminal ~ircuit a-b. The symbol 0 (zero) will be used to represent the hinderance of a closed circuit, and the s-ymbol 1 (unity) to represent ·the hinderance of an open circuit. trhus when the cir- \ cult a-b is open X ab = 1 and when closed X =O. ah Two hinderances X ab and Xed will oe said to be equal if \'Vhenever the circuit a-b is o'pen, tl1.8 circuit c-d is open, qnd. v'Jhenevc:r a-b is closed, c-d is closed. NoW let the symbol + (plUS) be defined to mean the series connection of the tvYO terr!linal circuits whose hinderanc as are ad1ied toge"thel' • Thus X a b • i~cd i:3 the ~li Ilderanc e 0 f the eireui t a.cd when band care co~nected together. Similarly the product of two hinderances (X ab • Xed) will be defined to mean the
Page 1 and 2: A SYl~:BOLIC OF Al~ALYSIS by Claude
Page 3 and 4: ACKNOvVLEDG1ffiNT The author is ind
Page 5: 2 COL~ac:s be ~ound. Although a sol
Page 9 and 10: • 6 3. a~ 0 + 0 = 0 A closed ~irc
Page 11 and 12: 8 equals 1 .. If X is the }1-ind-=J
Page 13 and 14: 10 Ole to thi s analogy any theorem
Page 15 and 16: 12 first note the following equatio
Page 17 and 18: l~ be obtained by replacin~ each va
Page 19 and 20: 16 y as the "XU of 17b. }IO\iV mult
Page 21 and 22: 18 III Multi-terminal end Non-aerie
Page 23 and 24: 20 The wye to delta tran sformation
Page 25 and 26: 22 Fig. 12 'The hinderance function
Page 27 and 28: This 8~a1n gives for the hinderance
Page 29 and 30: 26 I I I 1 X 12 X 13 • • •
Page 31 and 32: 28 Xi matrix the oroduct of the ele
Page 33 and 34: 30 50m~~~mes a relay X 1s to operat
Page 35 and 36: 32 where (~) : nl/k Hn-k) ~ is the
Page 37 and 38: This will be proved by mathematical
Page 39 and 40: 36 Dual l{et\vorks. The ne~et1ve of
Page 41 and 42: 38 In a eonstant-voltage relay syst
Page 43 and 44: identically the same. Thus XY + XZ
Page 45 and 46: 42 zero if either factor is zero, w
Page 47 and 48: varia "bles of Fig. 26, the termina
Page 49 and 50: 46 the circuits are- as shown in Fi
Page 51 and 52: !8 a time delay relB;T of sona so r
Page 53 and 54: 50- on the in genu~..ty 0 f the de
Page 55 and 56: 52 A Selective Circuit A relay 1:\
Page 57 and 58:
54 Zl z .~ "f'l, +--........~---" A
Page 59 and 60:
56 11Vhen z has opersted the lock u
Page 61 and 62:
58 A Vote Counting Circuit A circui
Page 63 and 64:
60 starting from the right, So is o
Page 65 and 66:
62 A Factor Table Machine A machine
Page 67 and 68:
ep11ssent1ng the numbe'!' being con
Page 69 and 70:
66 Usin~ the method of factorj.ng o
Page 71 and 72:
This design requires tnat t~e prime
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A Symbolic Analysis of Relay and Switching Circuits

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