RealView Compilation Tools Compiler Reference Guide - ARM ...

Using NEON Support
E.3 Intrinsics
The intrinsics described in this section map closely to NEON instructions. Each section
begins with a list of function prototypes, with a comment specifying an equivalent
assembler instruction. The compiler selects an instruction that has the required
semantics, but there is no guarantee that the compiler produces the listed instruction.
The intrinsics use a naming scheme that is similar to the NEON unified assembler
syntax. That is, each intrinsic has the form:
_
An additional q flag is provided to specify that the intrinsic operates on 128-bit vectors.
For example:
• vmul_s16, multiplies two vectors of signed 16-bit values.
This compiles to VMUL.I16 d2, d0, d1.
• vaddl_u8, is a long add of two 64-bit vectors containing unsigned 8-bit values,
resulting in a 128-bit vector of unsigned 16-bit values.
This compiles to VADDL.U8 q1, d0, d1.
Note
The intrinsic function prototypes in this section use the following type annotations:
__const(n) the argument n must be a compile-time constant
__constrange(min, max)
the argument must be a compile-time constant in the range min to max
__transfersize(n)
the intrinsic loads n bytes from this pointer.
E.3.1
Addition
These intrinsics add vectors. Each lane in the result is the consequence of performing
the addition on the corresponding lanes in each operand vector. The operations
performed are as follows:
• Vector add: vadd -> Vr[i]:=Va[i]+Vb[i] on page E-5
• Vector long add: vadd -> Vr[i]:=Va[i]+Vb[i] on page E-5
• Vector wide add: vadd -> Vr[i]:=Va[i]+Vb[i] on page E-5
• Vector halving add: vhadd -> Vr[i]:=(Va[i]+Vb[i])>>1 on page E-6
• Vector rounding halving add: vrhadd -> Vr[i]:=(Va[i]+Vb[i]+1)>>1 on
page E-6
E-4 Copyright © 2007, 2010 ARM Limited. All rights reserved. ARM DUI 0348A
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