Hybrid Integration - JePPIX
Hybrid Integration - JePPIX
Hybrid Integration - JePPIX
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Key Commercial Design Cell:<br />
High-Performance Detector & PLC <strong>Hybrid</strong> <strong>Integration</strong><br />
Photo-detector <strong>Integration</strong> via Turning Mirror<br />
TIA<br />
PIN<br />
Solder<br />
(deposited on<br />
PIN)<br />
Integrated PIN detector<br />
Submount<br />
PLC<br />
Waveguide<br />
PIN/APD<br />
TIA<br />
• Detector integration via turning mirror<br />
– High speed and CW tap<br />
• Detector mounted directly on PLC<br />
– ± 10µm alignment required<br />
– die tested prior to attach<br />
• TIA mounted on ceramic HIC<br />
– HICs tested prior to attach<br />
• IL < 0.2dB for 10G PIN<br />
16<br />
Highest Levels of Placement Accuracy for Highest Performance & Yield
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