Hybrid Integration - JePPIX

CHIPfab
Consortium for
Hybrid
Integrated
Photonics
T. L. Koch
Prof. of ECE & Physics
Director, Center for Optical Technologies
Lehigh University
Bethlehem, PA

Outline
• Photonic Integration: What is working & what is not working.
• What can a foundry approach bring to the table
• Monolithic vs. Hybrid
• Approach of CHIPfab consortium
• Examples of design cells
• CAD tool goals
• Expected deliverables

Historical State of Industry:
• Each new photonic application has been addressed through in-house
R&D to tweak design and process for highly optimized performance
• Results in lack of maturity in the underlying materials and process
platforms (compared to silicon electronics)
• Insufficient design commonality across customers, markets, and
applications has precluded the development of standardized integration
infrastructure
• Experience of R&D and manufacturing team is that each new product
will require extensive process development and stabilization
– Expensive and time consuming for both manufacturer and customer
• Huge $$$ Non-recurring engineering (NRE)
• Can only afford this engagement for customers with big proven markets and/or deep
pockets
• Can’t even talk seriously to new speculative customers, start-ups, entrepreneurs,
inhibits proliferation of new products and markets
• Leads to a “boutique industry” with little industry-wide shared
infrastructure and common design philosophy

Historical State of Industry:
• Each new photonic application has been addressed through in-house
R&D to tweak design and process for highly optimized performance
No. of Units
Performance
New design breakthrough
(MQW’s, etc.)
Why did this happen
• Huge leverage in core of
network for incremental
improvements in
performance
• High willingness to pay due
to tremendous cost sharing
• Not suitable for supporting
client applications,
incubating new markets, &
driving maturity of
technology

Photonic Integration Status in USA
• Strong historical foundation in photonic integration technology, strong role by
Bell Labs, much still retained at CyOptics, Inc.
• Subsequently, US private investment infrastructure has driven world-leading
advances in photonic integration technology:
– III-V (Infinera, but also Agility, Santur, etc., …)
– Si Photonics (Luxtera, Kotura, Lightwire, etc.)
• Issue: These start-ups have been necessarily extremely focused on relatively
narrow, near-term product opportunity to get revenue, return on investment, or
on captive, vertically integrated solution & market differentiation at system
level
• Still no incentive or infrastructure to share or re-use knowledge
– Technology not accessible to broad community for exploratory research and
development of new market opportunities
– Still many of the same challenges in long & expensive product development cycles
• Need to explore feasibility of different business model

What is a Foundry
Foundry:
– A manufacturing capability with the flexibility to produce
different configurations of design elements to create
different products serving different customers and different
markets
- and -
– Underlying processes are stabilized independently of any
particular configuration that may be currently in production
How is this done

CHIPfab
Consortium for
Hybrid
Integrated
Photonics

• Approach of consortium:
– Not a collection of technical capabilities & tools available for use
– Not a demonstration of the functional creativity achievable with PICs
– A collection of standard design cells that are stabilized by reasonably
high volume commercial products
• Provide end-user CAD tool interface based on combination of
physics-based & parametric modeling of standard design cells and
performance of their combined circuit functionality
• Capability will therefore be somewhat limited at first
– “Foundry design cells” (cells that can be realistically extracted and reused
AS-IS from commercial products
– plus –
What are the Goals
– “Research design cells” (best effort basis, initially no sustainable forces
to maintain stability)

What are the Goals
• Monolithic InP
• Si Photonics
• SiO 2 on Si PLC’s
– No room for religion in this endeavor. Many solutions are
inherently hybrid.

CyOptics Technology
Vertical Integration for Photonic Integrated Circuits
Assembly
Robotics
Package
A&T
InP - PLC Integration
precision placement
high levels of automation
Laser Array
InP Devices
DFB, EA, MZ, PIN/APD,
SOA, SSC, MUX
InP Process Elements
MQW active, SAG, butt joint regrowth,
ridge waveguides
broadband AR coatings
PLC Devices
Couplers, AWGs, SSC,
delay lines, EDWA,
switches, VOAs
PLC Process Elements
high ∆n, low loss waveguides
integrated turning mirror, Er doped
w’guides, low loss mode transitions
AWG MUX
10
All Key Technologies under One Roof

CyOptics has extensive monolithic & hybrid
PIC product capability
Example: 4x25GbE (4x10GbE) TOSA Options
TOSA: Monolithic Integration
Monitor PD DFB 25G EAM
4x25Gb/s EML
500um x 1500um
TOSA: Hybrid Integration
• Monolithic Integration in InP
of arrays of four (4)
− 25G DFB laser
− EA modulators
− Back-facet monitor diodes
with compact MMI coupler
Kotura Inc.
7800um x 3500um
25Gb/s DML
• Hybrid Integration of a 4
channel DFB (or EML) laser
array with SOI PLC Mux
2660 x 375 um
11
2000um x 375um

Examples of Monolithic & Hybrid Design Cells
Passives
Actives
Design Element Monolithic
Commercial
Design Cell
Hybrid
Commercial
Design Cell
Monolithic
Research
Design Cell
Low-Loss Waveguide
N-way Equal Splitter
Asymmetrical Split/Tap
AWG
Beam Expander
Turning Mirror
Fixed Grating
Polarization Splitter
Polarization Rotator
DFB laser
EA Modulator
MZ Modulator
VOA – EA based
SOA – Variable gain trim
SOA - Booster
SOA - Preamp
High Performance PIN
High Performance APD
Mon or Low Perf PIN
Tunable Phase Section
Tunable Grating

Transmitter Building Blocks
Array of
1.3um DMLs
Array of Spot
Size Converters
Optical Mux
Monolithically
Integrated in InP
Hybrid integration options
• CyOptics: butt-coupling
• Alternatives: lens coupling,
evanesence coupling

Key Commercial Design Cell:
Laser Array & PLC Hybrid Integration
Laser Array Integration via Passive Alignment
• Laser arrays flip chip
mounted onto PLC:
– Automated visioning
used to locate and align
fiducials on laser array
and PLC
– Array stays aligned
through soldering
process
• Passive alignment
keeps excess CE loss
< 2dB
Highest Levels of Placement Accuracy for Highest Performance & Yield

Receiver Building Blocks
Optical deMux
Array of turning
mirrors
Array of PIN
detectors
Array of TIAs
Hybrid integration options
• CyOptics: turning mirror
• Alternatives: lens coupling,
evanesence coupling

Key Commercial Design Cell:
High-Performance Detector & PLC Hybrid Integration
Photo-detector Integration via Turning Mirror
TIA
PIN
Solder
(deposited on
PIN)
Integrated PIN detector
Submount
PLC
Waveguide
PIN/APD
TIA
• Detector integration via turning mirror
– High speed and CW tap
• Detector mounted directly on PLC
– ± 10µm alignment required
– die tested prior to attach
• TIA mounted on ceramic HIC
– HICs tested prior to attach
• IL < 0.2dB for 10G PIN
16
Highest Levels of Placement Accuracy for Highest Performance & Yield

Silica PLC Examples
Hybrid Mixer for 100G PM-QPSK Rx
17

100 Gb/s PM-QPSK receiver
• Design integrates the best features
of two optical technologies
– Bulk optic polarization splitters
– Silica Planar Lightguide Circuit (PLC)
90°Hybrids
– Integrated balanced detectors on PLC
– OIF compliant form factor
• Features
– Compliant with OIF 100G Coherent Rx
Implementation Agreement
• Full functionality with integrated PBS
• Minimum package size
– Low cost structure hybrid integration
– Low profile surface mount package
Use this package as generic package for many CHIPfab prototype evaluations
• No custom package development in initial round
• Two-fiber capability, 40x27x7mm ample space, ample high-speed & low-speed lines

RSOFT Company Overview
Multi-Level Design Solutions For Photonic Applications
Network Planning
Optical System Simulation
MetroWAND
Artifex
OptSim ModeSYS
Passive and Active Device Design
BeamPROP FullWAVE BandSOLVE
GratingMOD DiffractMOD ModePROP
FemSIM LaserMOD MOST
rsoftdesign.com

Near-Term CAD Goals for Foundry Project
Phyics-based modeling of some design cells
Parametric-based modeling of some active cells
– Allows for future plug-ins of alternate manufacturing partner design
cells
Circuit-level & system-level performance simulation
Layout & design rule checking
– Mapping from functional layout to mask & fab processing will be
internal to manufacturing partner
rsoftdesign.com

AWG WDM Multiplexer (BPM)
AWG Layout:
Simulated Spectral Response:
rsoftdesign.com

SOI Optical Modulator
Modulator Layout
Carrier dependent index change
Phase Shift vs Bias Voltage
Frequency Response
Refs: A. Liu et al., Nature 427, pp. 615-618 (2004).
Soref and Bennett, IEEE JQE, 23, pp. 123-129 (1987).
RSoft Design Group, Photonics West, San Jose, CA, Jan. 2005
rsoftdesign.com

InGaAsP MQW FP Laser
Waveguide cross-section
Lattice temperature profile
L-I-V curves: experiment vs simulation
L-I-V curves: self-heating effects
Refs: Piprek et al, IEEE J. Quantum Electron. 36, 366 (2000).
B.Grote (RSoft Design Group) et al, Proc. SPIE Vol. 4986, pp. 413-422,
Physics and Simulation of Optoelectronic Devices XI (2003).
rsoftdesign.com

Circuit-Level Tool for Optoelectronic Subsystems
Modulator
Laser
rsoftdesign.com

Test & Measurement Equipment Interface
Simulating Optical Links with Dispersion Penalty from Time-resolved chirp (TRC) Measurements
Signal
Pattern Gen
GPIB
40GHz Scope
Pattern
Trigger
DUT
EDFA
Laser/optical modulator
TRC measurement
Interface to system simulation
PC/GPIB card
Simulation s/w
rsoftdesign.com

Integrated Framework: CAD Layout
3D PBG Structure
CMOS Device with Integrated Lenses
rsoftdesign.com

What are the Goals
• Near-term project strategy:
– Demo of particular functional product prototype for customer
using combination of commercialized cells
• New transceiver target, for example
– Show that same design cells, perhaps with addition of a few
other cells, can deliver quite different functionality with other
mainstream “product’ configurations
• Coherent functionality, OPLL, sensors, etc.
– Show that capabilities can be extended (functionality, speed,
spectral efficiency, etc., or driven to smaller footprint or power
(monolithic), etc., using “research cells”
– Provide “generic evaluation package” capability to take
foundry prototyping cost out (i.e., not targeting any optimized
product-specific foundry packaging at this point)

GOALS of Project
CHIPfab
Photonic Integration Foundry Attributes:
• Once realized, the principal features of the Photonics Integration Foundry
model should provide:
– Base technology in place providing high-performance design cells for hybrid
and monolithic integration supported by stabilized manufacturing processes;
– End user application developer CAD tools for design cell layout and
performance modeling;
• Virtual foundry design coordination team providing interface between applications
developers and industry manufacturing partners; users do not talk to manufacturers
• Some potential for shared wafer processing costs across multiple customers for costeffective
prototyping;
– Immediate pathway from prototyping to manufacture for dramatic reduction in
R&D cycles.