IntelR 80960 RN I/O Processor Datasheet

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Intel ® 80960RN I/O Processor Table 2 shows the available 80960JT instructions. Table 2. Instruction Set Data Movement Arithmetic Logical Bit, Bit Field and Byte Add Subtract Load Store Move Conditional Select Load Address Multiply Divide Remainder Modulo Shift Extended Shift Extended Multiply Extended Divide Add with Carry Subtract with Carry Conditional Add Conditional Subtract Rotate And Not And And Not Or Exclusive Or Not Or Or Not Nor Exclusive Nor Not Nand Set Bit Clear Bit Not Bit Alter Bit Scan For Bit Span Over Bit Extract Modify Scan Byte for Equal Byte Swap Comparison Branch Call/Return Fault Compare Conditional Compare Compare and Increment Compare and Decrement Test Condition Code Check Bit Unconditional Branch Conditional Branch Compare and Branch Call Call Extended Call System Return Branch and Link Conditional Fault Synchronize Faults Debug Processor Management Atomic Flush Local Registers Modify Trace Controls Mark Force Mark Modify Arithmetic Controls Modify Process Controls Halt System Control Cache Control Interrupt Control Atomic Add Atomic Modify 14 Data Sheet
Intel ® 80960RN I/O Processor 3.0 Package Information 3.1 Package Introduction The 80960RN processor is offered in a Perimeter Land Grid Array (PBGA) package. This is a perimeter array package with five rows of ball connections in the outer area of the package. See Figure 4 “540L H-PBGA Package Diagram (Bottom View)” on page 27. 3.1.1 Functional Signal Definitions This section defines the pins and signals in the following tables: • Table 3 “Pin Description Nomenclature” on page 16 • Table 4 “Memory Controller Signals” on page 17 • Table 5 “Primary PCI Bus Signals” on page 20 • Table 6 “Secondary PCI Arbiter Signals” on page 21 • Table 8 “Intel ® 80960Jx Core Signals and Configuration Straps” on page 24 • Table 9 “I 2 C, JTAG, Core Signals” on page 25 Data Sheet 15
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IntelR 80960 RN I/O Processor Datasheet

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