IntelR 80960 RN I/O Processor Datasheet

Intel ® 80960RN I/O Processor
Figures
Tables
1 Intel ® 80960RN Functional Block Diagram ..................................................... 8
2 Intel ® 80960JT Core Block Diagram ............................................................. 11
3 540L H-PBGA Package Diagram (Top and Side View) ................................ 26
4 540L H-PBGA Package Diagram (Bottom View) .......................................... 27
5 Thermocouple Attachment - A) No Heatsink / B) With Heatsink ................... 38
6 V CC5REF Current-Limiting Resistor................................................................ 43
7 V CCPLL Lowpass Filter .................................................................................. 43
8 P_CLK, TCK, DCLKIN, DCLKOUT Waveform............................................. 51
9 T OV Output Delay Waveform......................................................................... 51
10 T OF Output Float Waveform .......................................................................... 52
11 T IS and T IH Input Setup and Hold Waveform ................................................ 52
12 I 2 C Interface Signal Timings.......................................................................... 52
13 AC Test Load (all signals except SDRAM and Flash signals)....................... 53
1 Related Documentation................................................................................... 7
2 Instruction Set .............................................................................................. 14
3 Pin Description Nomenclature....................................................................... 16
4 Memory Controller Signals ............................................................................ 17
5 Primary PCI Bus Signals ............................................................................... 20
6 Secondary PCI Arbiter Signals...................................................................... 21
7 Secondary PCI Bus Signals .......................................................................... 22
8 Intel ® 80960Jx Core Signals and Configuration Straps................................. 24
9 I 2 C, JTAG, Core Signals ............................................................................... 25
10 540-Lead H-PBGA Package — Signal Name Order ..................................... 28
11 540-Lead H-PBGA Pinout — Ballpad Number Order.................................... 33
12 540-Lead H-PBGA Package Thermal Characteristics .................................. 39
13 Heat Sink Vendors and Contacts .................................................................. 40
14 Socket-Header Vendor.................................................................................. 40
15 Burn-in Socket Vendor .................................................................................. 40
16 Shipping Tray Vendor.................................................................................... 41
17 Logic Analyzer Interposer Vendor ................................................................. 41
18 JTAG Emulator Vendor ................................................................................. 41
19 Operating Conditions..................................................................................... 42
20 V DIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V)......... 43
21 DC Characteristics ........................................................................................ 44
22 I CC Characteristics ........................................................................................ 45
23 Input Clock Timings....................................................................................... 46
24 SDRAM Output Clock Timings ...................................................................... 46
25 PCI Signal Timings....................................................................................... 47
26 Intel ® 80960JN Core Signal Timings............................................................. 48
27 SDRAM / Flash Signal Timings..................................................................... 48
28 Boundary Scan Test Signal Timings ............................................................. 49
29 I2C Interface Signal Timings ......................................................................... 50
30 Device ID Registers...................................................................................... 54
Data Sheet 5