Microcontroller Solutions TechZone Magazine, April 2011 - Digikey

As shown in Figure 1, a typical 16-bit parallel fl ash memory delivers a
data transfer rate of 20 Megabytes per second. In systems that use
a 32-bit microcontroller with a 32-bit bus for the external memory
(like those from NXP), the designer can opt to use two 16-bit parallel
devices in combination for a rate of 40 Megabytes per second.
However, the added speed comes at a cost. The confi guration uses
two separate parallel fl ash memories, each housed in a package
with dozens of pins, and that may be more, in terms of package
size, pin count, and PCB space, than the designer can afford.
Serial fl ash, which typically uses the simple four-pin Serial
Peripheral Interface (SPI), can be a good alternative to parallel
fl ash when space, power, and cost are concerns, but it’s much
slower. Figure 1 shows that a typical SPI fl ash operating at 50
MHz transfers data at roughly 5 Megabytes per second (eight
times slower than a confi guration that uses two 16-bit parallel
devices). Another consideration is that the SPI interface on most
microcontrollers is connected to the MCU’s peripheral matrix, where
data has to be received by driver code and put into on-board RAM
before the processor can access it. This can slow things down,
since each read from serial fl ash has to go through an SPI software
layer. Depending on the application, using the standard SPI interface
for external memory may not be fast enough.
The new Quad SPI fl ash format, which uses a modifi ed, six-pin SPI
confi guration, is much faster than traditional SPI formats. As shown
in Figure 1, Quad SPI delivers a transfer rate of 40 Megabytes per
second, which is the same as using two 16-bit parallel devices.
Using Quad SPI is often much less expensive than the parallel
approach, since it uses far fewer pins and a much smaller package.
It would seem that Quad SPI fl ash would be a good replacement for
parallel fl ash in embedded systems, but the reality is that today’s
32-bit microcontrollers aren’t designed to support Quad SPI fl ash
at its maximum speeds. This is because the Quad SPI interface, like
the traditional SPI interface, is connected to the microcontroller’s
peripheral matrix.
Eliminating the tradeoff
NXP has developed a new peripheral function, called the SPI
Flash Interface (SPIFI) that essentially eliminates the parallel/
serial tradeoff. The patent-pending SPIFI (“spiffy”) peripheral lets
low-cost SPI and new Quad SPI fl ash memories appear in the
memory map of an ARM Cortex-M3 microcontroller, so the MCU
can use external SPI fl ash with only a minimal performance penalty
compared to external parallel fl ash memories. The complete
memory space of the external SPI fl ash appears in the MCU’s
memory map, so the microcontroller can access the external
memory directly, without a software API or library.
When used with a Quad SPI fl ash, for example, the SPIFI peripheral
supports a data transfer rate of up to 40 Megabytes per second.
The designer can choose a less expensive SPI fl ash device, with
its compact footprint and simple confi guration, but doesn’t have
to sacrifi ce performance. The designer may also be able to choose
a smaller, less costly microcontroller, because the system won’t
need a bulky interface for external parallel memory. The SPIFI
peripheral enables an embedded system that makes better use
of memory resources yet remains compact and effi cient while
lowering overall cost.
The SPIFI peripheral is a dedicated function that will initially
be available on the NXP LPC1800 series of ARM Cortex-M3
microcontrollers. It will also be available on upcoming product lines,
including the low-cost Cortex-M0 series and the Cortex M4 line of
digital serial controllers (DSCs).
SPIFI supports most serial fl ash devices on the market today
(including those with quad read/write capability) and is designed
for easy confi guration and programming. It uses four or six pins
(depending on the type of serial fl ash used), works with a small
register set, is optimized for effi cient memory transactions, and
uses software commands that reduce CPU overhead and streamline
memory interactions.
How SPIFI works
Figure 2 shows a block diagram of the SPIFI peripheral. The SPIFI
function is connected to the microcontroller’s Application Highspeed
Bus (AHB) matrix, which is used for the processor core and
the on-chip memories. The SPIFI peripheral presents the contents
of the external SPI fl ash in the microcontroller’s memory map. Once
the boot code in the on-chip ROM initializes the SPIFI interface, the
external SPI memory looks just like an on-chip memory to the core
processing unit.
Figure 2: Block diagram of the SPIFI peripheral.
Initialization sequence
All of the drivers required for the SPIFI interface are available in
ROM. For reading, only one call to a routine is made to initialize the
SPIFI peripheral. After the initialization sequence, the entire SPI fl ash
content is accessible as normal memory using byte, half word, and
word accesses by the processor and/or the DMA channels. Erasure
and programming are handled by a simple API call, which accesses
commands in ROM, so using the external SPI memory is as easy as
using on-chip fl ash memory.
Booting from SPIFI
For systems that need the microcontroller to boot from external
serial fl ash, the NXP LPC1800 microcontroller has been equipped
with a mechanism that includes SPIFI as a boot source. There
are two ways to select the boot source. The fi rst uses the
microcontroller pins to determine which interface to boot from, and
the second relies on the user to program a non-volatile location to
choose the interface. Using the non-volatile location saves the pins
from having dual-use functions.
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