Microcontroller Solutions TechZone Magazine, April 2011 - Digikey

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USB 3.0— Are We There Yet by John Donovan, Low-Power Design SuperSpeed USB may be slow out of the blocks, but with a 10x speed advantage and lower power profile than its predecessors, its compelling advantages make it look like a sure winner. Firewire 800 Firewire 400 0.2 0.2 49.6 31.6 39.3 39.9 40 73.6 74.5 75.8 If there was a universal serial bus in 1995, it was RS-232. Every PC in the world had one, although you could connect only one device to it at a time. Reconfiguring the port for new devices and/or applications required you to either be a “power user” or have an engineering degree. In January 1996, Intel introduced the Universal Serial Bus (USB), a bidirectional, low-cost, low- to mid-speed peripheral bus that could support as many as 127 devices, all of which could be added to the bus in “plug-and-play” (initially “plug-and-pray”) fashion. USB 1.0 supported a data transfer rate of 12 Mb/s, which worked well for disk drives. In 1998, USB 1.1 added a slower (1.5 Mb/s) rate to support keyboards, mice, and other human-interface devices (HID). Addressing the need for speed, the USB 2.0 specifi cation was released in 2000 and standardized in 2001, promising a data rate of 480 Mb/s. However, because of the overhead involved in the protocol and USB’s heavy reliance on the processor for transaction arbitration and scheduling, speeds closer to half that rate were more typical. Still, a theoretical 40x increase in bus speed in four years was pretty impressive. USB has since become the most successful PC peripheral interconnect ever defi ned, with over 10 billion USB 2.0 products installed today, a number that is rising rapidly. In-Stat predicts that nearly 4.5 billion USB ports will ship in 2014, of which 1.7 billion will support the new “SuperSpeed” USB 3.0 spec. Facing competition from other high-speed interconnect protocols (Figure 1), like 400 and 800 Mbps IEEE-1394 (FireWire) and HDMI (both of which targeted high-data rate streaming of video), the USB Implementers Forum (USB-IF) formalized the specifi cation for USB 3.0 in 2008, which promises a “SuperSpeed” data rate of 5 Gb/sec, a 10x improvement over USB 2.0. Design goals With USB 2.0 having become universal, the key goal was to make it faster. Since smart phone users can now sideload video fi les ten times faster, this will supposedly keep HDMI or FireWire sockets from proliferating on these devices. SATA 3Gbps (direct) eSATA USB 2.0 Access Time (ms) Average Read (MB/s) Read Burst (MB/s) Max Read (MB/s) USB 3.0 Min Read (MB/s) The primary goals for USB 3.0 are to: • Preserve the USB model of smart host and simple device. • Leverage the existing USB infrastructure. This means maintaining the same software architecture and easing the migration from legacy products. • Improve power management. • Maintain ease-of-use. • Preserve users’ investment in USB 2.0 devices. 0.1 0.1 0.2 0.1 0 50 29.8 36.3 36.8 36.8 Figure 1: Communications protocols speed comparison. With minor modifi cations, USB software stacks will continue to recognize the following three device classes: • Communications Device Class (CDC), which presents the USB port to an application as a standard COM port. Supporting bulk transfers, the CDC provides high-bandwidth with a reasonable amount of simplicity. • Human Interface Device (HID) Class, which supports mice, keyboards, touchscreens and other input devices. Bandwidth is limited to 64 kb/s. • Mass Storage Class (MSC), which supports moving large amounts of data to and from fl ash drives, digital cameras, and fl ash card readers. 69.8 99.6 91.7 119.8 120 121.1 194.5 227.9 216.3 184.4 196.8 213.1 100 150 200 250 64
USB 3.0 is clearly overkill for HID applications, but it’s definitely a new contender for embedded CDC and MSC applications, particularly those involving streaming high-definition video. Its power advantage over legacy USB makes it a serious consideration for portable devices. Architectural innovations Achieving a 10x speed improvement while reducing power consumption involved making serious architectural changes to both the protocol and associated hardware. At the same time, some tradeoffs (and clever workarounds) were necessary to maintain backward compatibility with legacy USB 2.0 products. For starters, USB 3.0 maintains the same tiered star topology as USB 2.0, maintaining compatibility by adding two more twisted pairs to the cable to supplement the USB 2.0 data pair, which is left untouched. The two additional signal pairs create a dual simplex SuperSpeed data path, with one pair for transmit and one for receive. This enables backward compatibility by including both SuperSpeed and non- SuperSpeed bus interfaces. Super Speed SuperSpeed Extended Connector(s) SuperSpeed Function High- Speed SuperSpeed Hub Non-SuperSpeed Full- Speed Non- SuperSpeed Function USB 2.0 Hub Low- Speed USB 3.0 Hub USB 3.0 Host Extended Connector(s) Non-SuperSpeed (USB 2.0) Composite Cable USB 3.0 Peripheral Device Note: Simultaneous operation of SuperSpeed and non-SuperSpeed modes is not allowed for peripheral devices Figure 2: USB 3.0 dual-bus architecture. (Used with permission from USB-IF). Polling is also eliminated. A USB 2.0 host continuously polls all peripheral devices to see if they have data to send to the host controller. All devices must therefore be on at all times, which not only wastes power but adds unnecessary traffic to the bus. In USB 3.0, polling is replaced by asynchronous notification. The host waits until an application tells it that there is a peripheral with data it needs to send to the host. The host then contacts that peripheral and requests that it send the data. When both are ready, the data is transferred. USB 2.0 is inherently a broadcast protocol. USB 3.0 uses directed data transfer to and from the host and only the target peripheral. Only that peripheral turns on its transceiver, while others on the bus remain in powered-down mode. Numerous innovations in the USB 3.0 architecture set it apart from its predecessors (Figure 3). Chip to Chip Port-to-Port End-to-End Host Device Driver/Application USB System Software Notifications Transaction Packets Transactions Data Packets Link Management Packets Pkt Delims 8b/10b encode/ decode Spread Clock CDR Link Control/Mgmt Link Cmds Scramble/ descramble LFPS Elasticity Buffer/Skips Hub Pipe Bundle (per Function Interface) Pkt Delims 8b/10b encode/ decode Default Control Pipe Spread Clock CDR Link Control/Mgmt Link Cmds Scramble/ descramble LFPS Elasticity Buffer/Skips Notifications PHY The SuperSpeed USB physical connection is comprised of two differential data pairs: one transmit path and one receive path, both operating at 5 GB/s. Each differential link is initialized by enabling its receiver termination. In the absence of signaling, low frequency periodic signaling (LFPS) is used to signal initialization and power management information. Data is packetized and passed directly to the intended receiver. Since USB 3.0 does not include a reference clock, each PHY has its own clock domain with spread spectrum clocking (SSC) modulation. The transmitter encodes data and control characters into symbols using an 8b/10b code, ensuring enough transitions that the receiver can accurately recover clock and data. Link layer SuperSpeed USB moves firmly into the realm of high-speed packet processing. The link layer handles link initialization and flow control, packet framing, link power management and error detection, and recovery. There are separate Link Management Packets (LMP), Transaction Packets (TP), Isochronous Timestamp Packets (ITP) and Data Packets (DP); all start with a distinct 14 byte header packet, consisting of 12 bytes of header information and a two byte CRC-16 code. This is not your dad’s USB. Protocol layer SuperSpeed USB is not a polled protocol, as devices may asynchronously transmit notifications to the host. Host-transmitted protocol packets are routed through intervening hubs, taking a direct path to a peripheral device. The transmitter can transmit multiple bursts of back-to-back sequences of data packets, while the receiver can simultaneously transmit data acknowledgements without interrupting the burst of data packets. This is a far more efficient use of bus bandwidth than the half-duplex, non-bursting nature of traffic on earlier USB buses. Table 1 summarizes the main differences between high-speed USB 2.0 and SuperSpeed 3.0. Power management First, SuperSpeed makes more power available to connected devices. The amount of power available on the USB bus (for recharging cell phones and other portable devices, for example) is increased from 5 V @ 500 mA in USB 2.0 to 5 V @ 900 mA for USB 3.0. This is a distinct advantage as more portable devices have come to rely on the USB bus not just for data transfer but also for battery recharging. Device Transaction Packets Function Device Transactions Data Packets Link Management Packets Pkt Delims 8b/10b encode/ decode Spread Clock CDR Link Control/Mgmt Link Cmds Scramble/ descramble LFPS Elasticity Buffer/Skips Figure 3: USB 3.0 logical architecture. (Used with permission from USB-IF). USB Function Power Management USB Device Power Management (Suspend) Localized Link Power Management Device or Host PROTOCOL LINK PHYSICAL www.digikey.ca/microcontroller 65
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Microcontroller Solutions TechZone Magazine, April 2011 - Digikey

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