Microcontroller Solutions TechZone Magazine, April 2011 - Digikey

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Table 1: USB 2.0 versus 3.0. (Used with permission from USB-IF). Characteristic USB 2.0 USB 3.0 Data rate Low-speed (1.5 Mbps), full-speed (12 Mbps), and high-speed (480 Mbps). Data interface Cable signal count Bus transaction protocol Power management Bus power Port state Data transfer types Half-duplex, two-wire differential signaling. Unidirectional data fl ow with negotiated directional bus transitions. Two: two for low-/full-/high- speed data path. Host directed, polled traffic flow. Packet traffic is broadcast to all devices. Port-level suspend with tow levels of entry/exit latency. Device-level power management. Support for low/high bus-powered devices with lower power limits for unconfigured and suspended devices. Port hardware detects connect events. System software uses port command to transitions the port into an enabled state (USB data communication fl ows). Four data transfer types: control, bulk, Interrupt, and Isochronous. SuperSpeed (5.0 Gpbs). Dual-simplex, four-wire differential signaling separate from USB 2.0 signaling. Simultaneous bi-directional data fl ows. Six: four for SuperSpeed data path. Two for non-SuperSpeed data path. Host directed, asynchronous traffi c fl ow. Packet traffi c is explicitly routed. Multi-level link power management supporting idle, sleep, and suspend states. Link-, Device-, and Functionlevel power management. Same as for USB 2.0 with a 50% increase for unconfigured power and an 80% increase for configured power. Port hardware detects connect events and brings the port into operational state ready for SuperSpeed data communication. USB 2.0 types with SuperSpeed constraints. Bulk has streams capability. More importantly, SuperSpeed USB enables considerable power savings by enabling both upstream and downstream ports to initiate lower power states on the link. In addition, multiple link power states are defi ned, enabling local power management control and, therefore, improved power usage effi ciency. Eliminating polling and broadcasting also went a long way toward reducing power requirements. Finally, the increased speed and effi ciency of USB 3.0 bus, combined with the ability to use data streaming for bulk transfers, further reduces the power profi le of these devices. Typically, the faster a data transfer completes, the faster system components can return to a low-power state. The USB-IF estimates the system power necessary to complete a 20 MB SuperSpeed data transfer will be 25 percent lower than is possible using USB 2.0. The SuperSpeed specifi cation brings over Link Power Management (LPM) from USB 2.0. LPM was fi rst introduced in the Enhanced Host Controller Interface (EHCI) to accommodate high-speed, PCI-based USB interfaces. Because of the diffi culty of implementing it, LPM was slow to appear in USB 2.0 devices. It is now required in USB 3.0 and for SuperSpeed devices supporting legacy high-speed peripherals. LPM is an adaptive power management model that uses link-state awareness to reduce power usage. LPM defi nes a fast host transition from an enabled state to L1 Sleep (~10 µs) or L2 Suspend (after 3 ms of inactivity). Return from L1 sleep varies from ~70 µs to 1 ms; return from L2 Suspend mode is OS dependent. The fast transitions and close control of power at the link level enables LPM to manage power consumption in SuperSpeed systems with greater precision than was previously possible. Link power management enables a link to be placed into a lower power state when the link partners are idle. The longer a pair of link partners remain idle, the deeper the power savings that can be achieved by progressing from UO (link active) to Ul (link standby with fast exit) to U2 (link standby with slower exit), and fi nally to U3 (suspend). Table 2 summarizes the logical link states. Table 2: Logical link states. (Used with permission from USB-IF). Link State Description Key Characteristics Device Clock Exit Latency U0 Link active - On N/A U1 Link idle, fast exit RX & TX quiesced On or off µs U2 Link idle, slow exit Clock gen circuit also On or off µs-ms quiesced U3 Suspend Portions of device power removed Off ms Most SuperSpeed devices, sensing inactivity on the link, will automatically reduce power to the PHY and transition from U0 to U1. Further inactivity will cause these devices to progressively lower power. The host or devices may further idle the link (U2), or the host may even suspend it (U3). Both devices and downstream ports can initiate Ul and U2 entry. Downstream ports have inactivity timers used to initiate Ul and U2 entry. Downstream port inactivity timeouts are programmed by system software. Devices may have additional information available that they can use to decide to initiate Ul or U2 entry more aggressively than inactivity timers. Devices can save significant power by initiating Ul or U2 more aggressively rather than waiting for downstream port inactivity timeouts. While the advantages of SuperSpeed USB are impressive, these devices are just beginning to appear in a world dominated by USB 2.0. For backward, compatibility SuperSpeed devices must support both USB 2.0 and 3.0 link speeds, maintaining separate controllers and PHYs for full-speed, high-speed and SuperSpeed links. By maintaining a parallel system to support legacy devices, SuperSpeed’s designers accepted higher cost and complexity as a price worth paying to avoid compromising the speed advantage of their new architecture. Adoption ramp No new standard, whatever its technical advantages, is adopted overnight. That is certainly true with USB 3.0, which needs to see a critical mass of devices in the fi eld before it will take off. Since consumers have long been content with USB 2.0, and since SuperSpeed devices will initially be more expensive, consumers will need to be convinced of compelling application benefi ts before it is likely to see broad adoption. Streaming multimedia is almost undoubtedly the killer app that will make this happen. One of the major things holding back USB 3.0 is the lack of support for it in core logic chipsets. Intel made much of its support for the standard at IDF 2009, and there was plenty of talk about it at the USB pavilion. However, at IDF 2010 Intel made no production silicon announcements—reportedly because of the diffi culty of developing bug-free silicon—and there does not appear to be any plan to include it in either Sandy Bridge or Atom processors for the next year or so. Intel’s apparent hesitation about supporting the standard will clearly stall its adoption in the marketplace and give Intel-based embedded developers pause about including it in their designs. Despite its recent hesitation, Intel will almost undoubtedly support USB 3.0 by next year. Meanwhile, the USB-IF announced more than 100 SuperSpeedcertifi ed products at IDF 2010, so this train, while still getting up to speed, has clearly left the station. It is now up to embedded developers to determine whether USB 3.0 is appropriate for their applications, and if so, to get on board. 66
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Microcontroller Solutions TechZone Magazine, April 2011 - Digikey

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