Microcontroller Solutions TechZone Magazine, April 2011 - Digikey

Physical interface
Figure 3 shows the physical interface of the SPIFI peripheral. It uses the
standard four pins for traditional SPI devices; when configured with Quad
SPI memory it uses an additional two pins to support the quad capability.
Figure 3: Physical interface of the SPIFI peripheral.
Different serial flash vendors and devices accept or require
different commands and command formats. The SPIFI peripheral provides
sufficient flexibility to be compatible with most common SPI flash and
includes extensions to help insure compatibility with future devices.
Reduced register set
A compact register set gives the SPIFI peripheral a considerable amount
of intelligence while keeping it simple to use. It takes just eight registers
to control the SPIFI function, interface with the external SPI memory,
store and retrieve data, and monitor operation. Since the built-in ROM
API governs setup, programming, and erasure, handling the external SPI
memory in an application is a matter of a few calls. As a result, the SPIFI
peripheral is simple to configure and easy to support in the application.
Software commands
The external memory responds to commands sent by the
microcontroller software and to commands automatically sent by the
SPIFI peripheral when its software reads the serial fl ash region of
the memory map. Commands are divided into fi elds called opcode,
address, intermediate, and data. The address, intermediate, and
data fi elds are optional depending on the opcode. Some memory
devices include a mode in which the opcode can be implied in Read
commands for higher performance. Data fi elds are further divided into
input and output data fi elds depending on the opcode. All commands
to the external SPI memory can be handled by calls to the ROM API.
The SPIFI ROM API driver lets the contents of the external SPI memory
be accessed using simple load commands, so the application code
remains compact and easy to write.
CPU-independent operation
The SPIFI software can read data from the external memory and write it
to RAM or a peripheral without involving the CPU. With microcontrollers
that have an integrated LCD controller, for example, this feature can be
used to enhance performance and save power. Images can be stored in
the external memory and fetched by the LCD controller. Since the LCD
controller reads most of its data from sequential addresses, the SPIFI
peripheral can pre-fetch the addresses so they’re ready when needed,
with essentially no wait states. The entire operation can happen without
getting the CPU involved, and there’s no need to load the images into
on-chip RAM before the LCD controller fetches them. That means the
system can use a microcontroller with less on-chip RAM, or can free
up its existing RAM for other tasks. Also, since the images are fetched
directly by the LCD controller, the LCD display can refresh graphics
faster, so simple operations like opening and closing windows appear
smoother. Also, to save power, the system can use a slower clock speed
without having a noticeable impact on the display’s performance.
Direct execution
From a software point of view, the microcontroller can execute code
directly from the external SPI memory. Direct execution can be helpful
when using in-fi eld upgrades or when replacing functions originally
shipped in on-chip fl ash. Validated upgrade code can be placed in the
external fl ash. If, for example, the system’s function addresses are in
a table stored in on-chip fl ash, the table can be reprogrammed with
the address of the routine now housed in external fl ash. Alternatively,
if the page containing the start of the original routine is stored in
on-chip fl ash, the page can be updated with a branch long jump to
the new routine in external fl ash. In either case, the new code doesn’t
need to be loaded into the on-chip RAM to execute, because the SPIFI
peripheral allows direct execution from the external memory.
Executing code from an external memory is never as fast as using
on-chip memory. The SPIFI peripheral isn’t intended for use with
real-time functions that require peak performance but, for less critical
code sequences, SPIFI can be a very attractive option.
Write-while-execute functions
The SPIFI supports write-while-execute functionality, which means it
can program or erase the external memory simply and quickly, even
when the processor is executing code from on-chip fl ash. Since the
SPIFI peripheral can run on its own, without interaction from the CPU,
the system can perform its functions without interruption while the
serial fl ash is being reprogrammed.
This feature can be used to perform software upgrades in the fi eld,
because the system can write to the external memory without
interrupting critical application code. In a smart meter, for example,
the metering function needs to operate continuously, even during a
software upgrade. With SPIFI, the utility company can confi gure the
system to write any new code to external fl ash, without interrupting
the active metering function, and can then integrate the new code
into the system. Similarly, in a system that has a USB port, new code
can be placed on a portable USB drive and transferred to the external
fl ash without interrupting critical operations.
Conclusions
NXP’s new SPI Flash Interface (SPIFI), a patent-pending feature initially
available on its new ARM-based LPC1800 Cortex-M3 microcontrollers,
lets external serial fl ash memory appear in the microcontroller’s
memory map, so it can be read like on-chip memory. This gives
designers access to a large amount of external fl ash memory while
reducing system costs and minimizing the design footprint.
The SPIFI peripheral creates a way for designers to use a small,
inexpensive serial flash where they might previously have needed to use
a larger, more expensive parallel flash to meet the system’s performance
requirements. Designers can take advantage of the many benefits of
serial flash — low-cost, small size, simple configuration — without
making large sacrifices in performance. SPIFI also lets designers opt for
a microcontroller without a parallel interface, for a smaller, less expensive
design that still delivers the required performance.
The NXP roadmap for SPIFI includes migration to other Cortex-M
families, including the low-cost Cortex-M0 series and the upcoming
Cortex-M4 series of Digital Signal Controllers.
www.digikey.ca/microcontroller
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