ARM11 MPCore Processor - ARM Information Center

More documents

Recommendations

Info

MPCore Private Memory Region Table 9-2 SCU register definition (continued) Offset Name Reset value Type Description 0x1C Monitor Counter 0 0x00000000 R/W See Count registers, MN0-MN7 on page 9-13 0x20 Monitor Counter 1 0x00000000 R/W 0x24 Monitor Counter 2 0x00000000 R/W 0x28 Monitor Counter 3 0x00000000 R/W 0x2C Monitor Counter 4 0x00000000 R/W 0x30 Monitor Counter 5 0x00000000 R/W 0x34 Monitor Counter 6 0x00000000 R/W 0x38 Monitor Counter 7 0x00000000 R/W 0x3C - 0xFC Reserved - - RAZ 9.1.2 SCU Control Register The SCU Control Register enables the SCU and controls its behavior. It must be accessed using a read-modify-write sequence. Figure 9-1 shows the format of the SCU Control Register. Figure 9-1 SCU Control Register format 9-4 Copyright © 2005, 2006, 2008 ARM Limited. All rights reserved. ARM DDI 0360E
MPCore Private Memory Region Table 9-3 shows the SCU Control Register bit assignments. Table 9-3 SCU Control Register bit assignments Bits Field Description [31:13] Reserved SBZ [12:9] CPU peripheral interface aliasing control bits [8:5] CPU interrupt interface aliasing control bits [4:1] SCU register access control bits 1 = CPUn, controlled by bit n+9, can access aliased timer and watchdog registers in the offset range 0x0700 to 0x0A0FF of the MPCore private memory region as described in Table 9-1 on page 9-2. 0 = CPUn cannot access aliased region. It can only access its own timer and watchdog registers through the dedicated offset range 0x0600 to 0x06FF as described in Table 9-1 on page 9-2. 1 = CPUn, controlled by bit n+5, can access aliased interrupt interface registers in the offset range 0x0200 to 0x050FF of the MPCore private memory region as described in Table 9-1 on page 9-2. 0 = CPUn cannot access aliased region. It can only access its own interrupt interface registers through the dedicated offset range 0x0100 to 0x01FF as described in Table 9-1 on page 9-2. 1 = CPUn, controlled by bit n+1, can write to SCU-specific registers described in Table 9-2 on page 9-3. By default, all CPUs can access SCU registers. 0 = CPU cannot modify SCU specific register. Clearing these bits enables you to define one or more master CPUs that control the SCU registers. This avoids unexpected changes in SCU configuration, particularly if some CPUs are in SMP mode and others are in AMP mode. There is a mechanism that prevents all bits being cleared at the same time. [0] SCU En 1 SCU is enabled, coherency is maintained between MP11 CPUs Level 1 data side caches. 0 SCU is disabled, coherency is not maintained between MP11 CPUs Level 1 data side caches. In an ARM11 MPCore single CPU configuration, writing to this bit has no effect and it is always read as zero. 9.1.3 SCU Configuration Register The SCU Configuration Register is read-only. Figure 9-2 on page 9-6 shows the format for this register. ARM DDI 0360E Copyright © 2005, 2006, 2008 ARM Limited. All rights reserved. 9-5
Page 1 and 2:
ARM11 MPCore Processor Revision: r1
Page 3 and 4:
This document is intended only to a
Page 5 and 6:
Contents ARM11 MPCore Processor Tec
Page 7 and 8:
Contents 6.5 Memory Barriers ......
Page 9 and 10:
Contents 16.8 VFP11 treatment of br
Page 11 and 12:
List of Tables ARM11 MPCore Process
Page 13 and 14:
List of Tables Table 5-2 Access Per
Page 15 and 16:
List of Tables Table 17-2 VFP11 MRC
Page 17 and 18:
List of Figures ARM11 MPCore Proces
Page 19 and 20:
List of Figures Figure 3-39 Context
Page 21 and 22:
List of Figures Figure 16-3 LS pipe
Page 23 and 24:
Preface This preface introduces the
Page 25 and 26:
Preface Chapter 5 Memory Management
Page 27 and 28:
Preface bold monospace monospace mo
Page 29 and 30:
Preface ARM Limited periodically pr
Page 31 and 32:
Chapter 1 Introduction This chapter
Page 33 and 34:
Introduction
Page 35 and 36:
Introduction 1.3 MP11 CPU overview
Page 37 and 38:
Introduction • MAC operations. Mu
Page 39 and 40:
Introduction Return stack A three-e
Page 41 and 42:
Introduction Because cache lookups
Page 43 and 44:
Introduction 1.4 Debug and programm
Page 45 and 46:
Introduction The VFP supports a wid
Page 47 and 48:
Introduction Interrupt generation e
Page 49 and 50:
Introduction Shutdown mode This mod
Page 51 and 52:
Introduction The MBIST solution you
Page 53 and 54:
Introduction By overlapping the var
Page 55 and 56:
Introduction Ex1 Ex2 Ex3 Sh ALU Sat
Page 57 and 58:
Introduction 1.8.1 Instruction prog
Page 59 and 60:
Introduction Ex1 Ex2 Ex3 Sh 5 ALU 6
Page 61 and 62:
Introduction Thumb therefore offers
Page 63 and 64:
Chapter 2 Programmer’s Model This
Page 65 and 66:
Programmer’s Model 2.2 Processor
Page 67 and 68:
Programmer’s Model 2.4 Data types
Page 69 and 70:
Programmer’s Model Bit Higher add
Page 71 and 72:
Programmer’s Model 4. If an exter
Page 73 and 74:
Programmer’s Model 2.8 Registers
Page 75 and 76:
Programmer’s Model ARM state gene
Page 77 and 78:
Programmer’s Model Thumb state ge
Page 79 and 80:
Programmer’s Model 2.9 The progra
Page 81 and 82:
Programmer’s Model To determine t
Page 83 and 84:
Programmer’s Model • For signed
Page 85 and 86:
Programmer’s Model Table 2-4 PSR
Page 87 and 88:
Programmer’s Model 2.10 Exception
Page 89 and 90:
Programmer’s Model Table 2-5 Exce
Page 91 and 92:
Programmer’s Model 2.10.6 Fast in
Page 93 and 94:
Programmer’s Model • all aborts
Page 95 and 96:
Programmer’s Model 2.10.12 Breakp
Page 97 and 98:
Programmer’s Model Precise Data A
Page 99 and 100:
Programmer’s Model Where: Is t
Page 101 and 102:
Programmer’s Model The pair of re
Page 103 and 104:
Programmer’s Model 2.11.5 STREXH
Page 105 and 106:
Programmer’s Model Specifies th
Page 107 and 108:
Programmer’s Model • ClearByAdd
Page 109 and 110:
Programmer’s Model 31 28 27 20 19
Page 111 and 112:
Programmer’s Model All others val
Page 114 and 115:
Control Coprocessor CP15 3.1 About
Page 116 and 117:
Control Coprocessor CP15 3.2 CP15 r
Page 118 and 119:
Control Coprocessor CP15 Function R
Page 120 and 121:
Control Coprocessor CP15 Table 3-2
Page 122 and 123:
Page 124 and 125:
Control Coprocessor CP15 3.4 Regist
Page 126 and 127:
Control Coprocessor CP15 Bit Name F
Page 128 and 129:
Control Coprocessor CP15 Figure 3-5
Page 130 and 131:
Control Coprocessor CP15 31 8 7 4 3
Page 132 and 133:
Page 134 and 135:
Control Coprocessor CP15 31 28 27 2
Page 136 and 137:
Control Coprocessor CP15 Bit Name V
Page 138 and 139:
Control Coprocessor CP15 Instructio
Page 140 and 141:
Control Coprocessor CP15 Instructio
Page 142 and 143:
Control Coprocessor CP15 • a 32 b
Page 144 and 145:
Page 146 and 147:
Control Coprocessor CP15 The Auxili
Page 148 and 149:
Control Coprocessor CP15 Note In AM
Page 150 and 151:
Page 152 and 153:
Control Coprocessor CP15 The Transl
Page 154 and 155:
Page 156 and 157:
Control Coprocessor CP15 3.4.15 c5,
Page 158 and 159:
Control Coprocessor CP15 Writing CP
Page 160 and 161:
Control Coprocessor CP15 As such, D
Page 162 and 163:
Control Coprocessor CP15 31 30 29 S
Page 164 and 165:
Control Coprocessor CP15 Invalidate
Page 166 and 167:
Page 168 and 169:
Control Coprocessor CP15 Note The p
Page 170 and 171:
Control Coprocessor CP15 A locking
Page 172 and 173:
Control Coprocessor CP15 0 Means su
Page 174 and 175:
Page 176 and 177:
Page 178 and 179:
Control Coprocessor CP15 You must n
Page 180 and 181:
Control Coprocessor CP15 • detect
Page 182 and 183:
Control Coprocessor CP15 There is a
Page 184 and 185:
Control Coprocessor CP15 MRC p15, 0
Page 186 and 187:
Page 188 and 189:
Page 190 and 191:
Control Coprocessor CP15 3.5 Summar
Page 192 and 193:
Page 194 and 195:
Control Coprocessor CP15 3-82 Copyr
Page 196 and 197:
Unaligned and Mixed-Endian Data Acc
Page 198 and 199:
Page 200 and 201:
Page 202 and 203:
Page 204 and 205:
Page 206 and 207:
Page 208 and 209:
Page 210 and 211:
Page 212 and 213:
Page 214 and 215:
Page 216 and 217:
Page 218 and 219:
Page 220 and 221:
Page 222 and 223:
Memory Management Unit 5.1 About th
Page 224 and 225:
Memory Management Unit 5.2 TLB orga
Page 226 and 227:
Memory Management Unit 5.2.5 Cohere
Page 228 and 229:
Memory Management Unit Small pages
Page 230 and 231:
Memory Management Unit • No memor
Page 232 and 233:
Memory Management Unit One program
Page 234 and 235:
Memory Management Unit The AP bits
Page 236 and 237:
Memory Management Unit Table 5-3 TE
Page 238 and 239:
Memory Management Unit 5.6.3 Page t
Page 240 and 241:
Memory Management Unit 5.7 Memory a
Page 242 and 243:
Memory Management Unit All explicit
Page 244 and 245:
Memory Management Unit ARM11 MPCore
Page 246 and 247:
Memory Management Unit Ordering req
Page 248 and 249:
Memory Management Unit 2. If A1 and
Page 250 and 251:
Memory Management Unit 5.7.6 Backwa
Page 252 and 253:
Memory Management Unit External abo
Page 254 and 255:
Memory Management Unit Virtual addr
Page 256 and 257:
Memory Management Unit 5.9.2 Alignm
Page 258 and 259:
Memory Management Unit 5.10 Fault s
Page 260 and 261:
Memory Management Unit 5.11 Hardwar
Page 262 and 263:
Memory Management Unit Figure 5-4 s
Page 264 and 265:
Memory Management Unit • Three ac
Page 266 and 267:
Memory Management Unit Translation
Page 268 and 269:
Memory Management Unit 5.12 MMU des
Page 270 and 271:
Memory Management Unit 5.12.2 First
Page 272 and 273: Memory Management Unit Translation
Page 274 and 275: Memory Management Unit Second-level
Page 276 and 277: Memory Management Unit Second-level
Page 278 and 279: Memory Management Unit Translation
Page 280 and 281: Memory Management Unit Register CRn
Page 282 and 283: Memory Management Unit Register CRn
Page 284 and 285: Memory Management Unit 5.14 MMU and
Page 286 and 287: Program Flow Prediction 6.1 About p
Page 288 and 289: Program Flow Prediction 6.2 Branch
Page 290 and 291: Program Flow Prediction 6.2.3 Stati
Page 292 and 293: Program Flow Prediction 6.3 Return
Page 294 and 295: Program Flow Prediction 6.5 Memory
Page 296 and 297: Program Flow Prediction 6-12 Copyri
Page 298 and 299: Level 1 Memory System 7.1 Coherency
Page 300 and 301: Level 1 Memory System This removes
Page 302 and 303: Level 1 Memory System • All cacha
Page 304 and 305: Level 1 Memory System 7.2.7 Linefil
Page 306 and 307: Level 1 Memory System 7.4 TLB Organ
Page 308 and 309: Level 1 Memory System Supersections
Page 310 and 311: Level 2 Memory System 8.1 MPCore Le
Page 312 and 313: Level 2 Memory System • Bit 2 and
Page 314 and 315: Level 2 Memory System 8.2 L2 exclus
Page 316 and 317: Level 2 Memory System x = address s
Page 318 and 319: Level 2 Memory System 8-10 Copyrigh
Page 320 and 321: MPCore Private Memory Region 9.1 Ab
Page 324 and 325: MPCore Private Memory Region
Page 326 and 327: MPCore Private Memory Region MP11 C
Page 328 and 329: MPCore Private Memory Region Table
Page 330 and 331: MPCore Private Memory Region Table
Page 332 and 333: MPCore Private Memory Region 9-14 C
Page 334 and 335: MPCore Distributed Interrupt Contro
Page 364 and 365: Clocking, Resets, and Power Managem
Page 372 and 373:
Clocking, Resets, and Power Managem
Page 374 and 375:
Page 376 and 377:
Page 378 and 379:
Debug 12.1 Debug systems The ARM11
Page 380 and 381:
Debug 12.2 About the debug unit The
Page 382 and 383:
Debug 12.3 Debug registers Table 12
Page 384 and 385:
Debug 12.3.2 CP14 c0, Debug ID Regi
Page 386 and 387:
Debug Breakpoint hit in Halt mode D
Page 388 and 389:
Debug Table 12-4 Debug Status and C
Page 390 and 391:
Debug 31 0 Data Table 12-5 shows th
Page 392 and 393:
Debug Breakpoint debug events gener
Page 394 and 395:
Debug Table 12-9 Breakpoint Control
Page 396 and 397:
Debug • If a BRP (holding an IVA)
Page 398 and 399:
Debug Table 12-12 Watchpoint Contro
Page 400 and 401:
Debug 12.5 CP14 debug instructions
Page 402 and 403:
Debug Table 12-14 Debug instruction
Page 404 and 405:
Debug 12.6.2 External debug request
Page 406 and 407:
Debug Table 12-16 shows the setting
Page 408 and 409:
Debug • the CP15 IFSR register is
Page 410 and 411:
Debug • A DBGTAP debugger can for
Page 412 and 413:
Debug SWI If this instruction is ex
Page 414 and 415:
Debug 12.10 Debugging in a system w
Page 416 and 417:
Debug You can program a breakpoint
Page 418 and 419:
Debug • BCRa[20] enable linking b
Page 420 and 421:
Debug 3. Read the word from the rDT
Page 422 and 423:
Debug • Setting software breakpoi
Page 424 and 425:
Debug 12-48 Copyright © 2005, 2006
Page 426 and 427:
Debug Test Access Port 13.1 Debug T
Page 428 and 429:
Debug Test Access Port 13.3 Enterin
Page 430 and 431:
Debug Test Access Port 13.5 DBGTAP
Page 432 and 433:
Debug Test Access Port 13.6 Debug r
Page 434 and 435:
Debug Test Access Port section. Thi
Page 436 and 437:
Debug Test Access Port Description
Page 438 and 439:
Debug Test Access Port Description
Page 440 and 441:
Debug Test Access Port DBGTAP debug
Page 442 and 443:
Debug Test Access Port — rDTR ove
Page 444 and 445:
Debug Test Access Port A typical se
Page 446 and 447:
Debug Test Access Port Interpreting
Page 448 and 449:
Debug Test Access Port this bit is
Page 450 and 451:
Debug Test Access Port 14. The leas
Page 452 and 453:
Debug Test Access Port 5. The least
Page 454 and 455:
Debug Test Access Port Target to ho
Page 456 and 457:
Debug Test Access Port 16. Scan_N i
Page 458 and 459:
Debug Test Access Port ITRsel 1. Sc
Page 460 and 461:
Debug Test Access Port 13.8.2 Gener
Page 462 and 463:
Debug Test Access Port b. Transfer
Page 464 and 465:
Debug Test Access Port 11. Wait unt
Page 466 and 467:
Debug Test Access Port 13.8.10 Read
Page 468 and 469:
Debug Test Access Port 6. Scan out
Page 470 and 471:
Debug Test Access Port 4. Now check
Page 472 and 473:
Debug Test Access Port 13.9.3 Setti
Page 474 and 475:
Debug Test Access Port 13-50 Copyri
Page 476 and 477:
Trace Interface Port 14.1 About the
Page 478 and 479:
Trace Interface Port Table 14-2 ETM
Page 480 and 481:
Trace Interface Port 14.1.3 Data va
Page 482 and 483:
Trace Interface Port 14.1.5 Coproce
Page 484 and 485:
Trace Interface Port 14-10 Copyrigh
Page 486 and 487:
Cycle Timings and Interlock Behavio
Page 488 and 489:
Page 490 and 491:
Page 492 and 493:
Page 494 and 495:
Page 496 and 497:
Page 498 and 499:
Page 500 and 501:
Page 502 and 503:
Page 504 and 505:
Page 506 and 507:
Page 508 and 509:
Page 510 and 511:
Page 512 and 513:
Page 514 and 515:
Page 516 and 517:
Page 518 and 519:
Introduction to VFP 16.1 About the
Page 520 and 521:
Introduction to VFP 16.3 Coprocesso
Page 522 and 523:
Introduction to VFP Decode Read por
Page 524 and 525:
Introduction to VFP 4. The sum is r
Page 526 and 527:
Introduction to VFP Fetch Decode Is
Page 528 and 529:
Introduction to VFP 16.5 Modes of o
Page 530 and 531:
Introduction to VFP • the VFP11 c
Page 532 and 533:
Introduction to VFP 16.7 Parallel e
Page 534 and 535:
Introduction to VFP 16.9 Writing op
Page 536 and 537:
Introduction to VFP 16-20 Copyright
Page 538 and 539:
VFP Register File 17.1 About the re
Page 540 and 541:
VFP Register File The IEEE 754 stan
Page 542 and 543:
VFP Register File 17.4 Loading oper
Page 544 and 545:
VFP Register File 17.5 Maintaining
Page 546 and 547:
VFP Register File For double-precis
Page 548 and 549:
VFP Register File Example 17-1 Regi
Page 550 and 551:
VFP Register File FMULD D13, D9, D2
Page 552 and 553:
VFP Register File Table 17-10 descr
Page 554 and 555:
VFP Programmer’s Model 18.1 About
Page 556 and 557:
VFP Programmer’s Model To execute
Page 558 and 559:
VFP Programmer’s Model Table 18-2
Page 560 and 561:
VFP Programmer’s Model FMRS Rx,Sn
Page 562 and 563:
VFP Programmer’s Model 18.3 ARMv5
Page 564 and 565:
VFP Programmer’s Model Architectu
Page 566 and 567:
VFP Programmer’s Model 31 28 27 2
Page 568 and 569:
VFP Programmer’s Model 18.4 VFP11
Page 570 and 571:
VFP Programmer’s Model The follow
Page 572 and 573:
VFP Programmer’s Model Table 18-6
Page 574 and 575:
VFP Programmer’s Model The rules
Page 576 and 577:
VFP Programmer’s Model Bit Name D
Page 578 and 579:
VFP Programmer’s Model • access
Page 580 and 581:
VFP Programmer’s Model 18-28 Copy
Page 582 and 583:
VFP Instruction Execution 19.1 Abou
Page 584 and 585:
VFP Instruction Execution 19.3 Inte
Page 586 and 587:
VFP Instruction Execution In Exampl
Page 588 and 589:
VFP Instruction Execution 19.6 Oper
Page 590 and 591:
VFP Instruction Execution FADDS S8,
Page 592 and 593:
VFP Instruction Execution In RunFas
Page 594 and 595:
VFP Instruction Execution FMULD D6,
Page 596 and 597:
VFP Instruction Execution FADDS S1,
Page 598 and 599:
VFP Instruction Execution Table 19-
Page 600 and 601:
VFP Instruction Execution 19.9 Reso
Page 602 and 603:
VFP Instruction Execution 19.9.3 Sh
Page 604 and 605:
VFP Instruction Execution Example 1
Page 606 and 607:
VFP Instruction Execution Table 19-
Page 608 and 609:
VFP Exception Handling 20.1 About e
Page 610 and 611:
VFP Exception Handling instruction
Page 612 and 613:
VFP Exception Handling If one or mo
Page 614 and 615:
VFP Exception Handling 20.4 Excepti
Page 616 and 617:
VFP Exception Handling 20.4.4 Examp
Page 618 and 619:
VFP Exception Handling UFC 0 OFC 0
Page 620 and 621:
VFP Exception Handling 20.5 Input S
Page 622 and 623:
VFP Exception Handling The VFP11 co
Page 624 and 625:
VFP Exception Handling 20.7 Divisio
Page 626 and 627:
VFP Exception Handling Table 20-6 R
Page 628 and 629:
VFP Exception Handling When the FZ
Page 630 and 631:
VFP Exception Handling 20.11 Input
Page 632 and 633:
VFP Exception Handling 20.12.1 FADD
Page 634 and 635:
VFP Exception Handling b. SP = sing
Page 636 and 637:
VFP Exception Handling the minimum
Page 638 and 639:
VFP Exception Handling 20.12.10FTOU
Page 640 and 641:
VFP Exception Handling Table 20-13
Page 642 and 643:
VFP Exception Handling 20-36 Copyri
Page 644 and 645:
Signal Descriptions A.1 AXI interfa
Page 646 and 647:
Signal Descriptions Table A-3 Maste
Page 648 and 649:
Signal Descriptions Table A-7 shows
Page 650 and 651:
Signal Descriptions A.2 Interrupt l
Page 652 and 653:
Signal Descriptions A.4 MBIST inter
Page 654 and 655:
Signal Descriptions Table A-14 Powe
Page 656 and 657:
Signal Descriptions Table A-15 Misc
Page 658 and 659:
Signal Descriptions A.8 ETM interfa
Page 660 and 661:
Signal Descriptions A-18 Copyright
Page 662 and 663:
AC Characteristics B.1 MPCore timin
Page 664 and 665:
AC Characteristics System CLK or HC
Page 666 and 667:
MBIST Controller and Dispatch Unit
Page 668 and 669:
Page 670 and 671:
Page 672 and 673:
Page 674 and 675:
Page 676 and 677:
Page 678 and 679:
Page 680 and 681:
Page 682 and 683:
Page 684 and 685:
Page 686 and 687:
Page 688 and 689:
Page 690 and 691:
Page 692 and 693:
Scan chain ordering with RVI D.1 Sc
Page 694 and 695:
Scan chain ordering with RVI D-4 Co
Page 696 and 697:
IEM E.1 Purpose of IEM The purpose
Page 698 and 699:
IEM E.2 About AXI register slices T
Page 700 and 701:
IEM E-6 Copyright © 2005, 2006, 20
Page 702 and 703:
Glossary Advanced eXtensible Interf
Page 704 and 705:
Glossary ATB bridge A synchronous A
Page 706 and 707:
Glossary Write interleave capabilit
Page 708 and 709:
Glossary Boundary scan chain Branch
Page 710 and 711:
Glossary Cache way A group of cache
Page 712 and 713:
Glossary Data cache DBGTAP A block
Page 714 and 715:
Glossary Enabled exception Endianne
Page 716 and 717:
Glossary Fm Fn Formatter Fraction F
Page 718 and 719:
Glossary Instruction cache A block
Page 720 and 721:
Glossary Memory Protection Unit (MP
Page 722 and 723:
Glossary Remapping Replicator Reser
Page 724 and 725:
Glossary behavior of the device. It
Page 726 and 727:
Glossary exception processing. The
Page 728 and 729:
Glossary Write-back (WB) Write buff
Page 730:
Glossary Glossary-30 Copyright © 2
show all

ARM11 MPCore Processor - ARM Information Center

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?